Patents by Inventor Kunihiro Miyazaki

Kunihiro Miyazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110034015
    Abstract: According to one embodiment, a heat treatment apparatus includes a light emitting unit to emit light to irradiate a wafer, a processing unit with a stage section and a control unit. The control unit implements a first irradiation to irradiate the light onto the wafer. After the first irradiation, the control unit changes at least one selected from a disposition of the wafer, a distribution of an intensity of the light on a major surface of the stage section along a circumferential edge direction of the wafer, and a distribution of a temperature of the wafer in a supplemental heating by the stage section along a circumferential edge direction of the wafer. After the changing, the control unit implements a second irradiation to irradiate the light onto the wafer. Durations of the first irradiation and the second irradiation are shorter than a time necessary for the changing.
    Type: Application
    Filed: June 8, 2010
    Publication date: February 10, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenichi Yoshino, Takayuki Ito, Kunihiro Miyazaki
  • Patent number: 7875557
    Abstract: A semiconductor substrate treating method is disclosed that can selectively remove contaminants or unnecessary substances present on the surface of a semiconductor substrate. Also disclosed are a semiconductor component of enhanced reliability produced by this method and an electronic appliance incorporating the semiconductor component. The semiconductor substrate treating method comprises the step of treating a semiconductor substrate with a treating fluid containing NH4OH and HF wherein the relationships 0.30?X/Y?0.78 and 0.03?Y?6.0 are satisfied, where X represents a concentration [mol/L] of NH4OH in the treating fluid and Y represents a concentration [mol/L] of HF in the treating fluid. Preferably, the treating fluid is substantially free from H2O2. The semiconductor substrate has a surface, at least a part of which is composed of high melting point metal.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: January 25, 2011
    Assignees: Seiko Epson Corporation, Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Matsuo, Kunihiro Miyazaki, Toshiki Nakajima
  • Patent number: 7875527
    Abstract: A trench is formed on a semiconductor substrate with a first insulation film patterned on the semiconductor substrate as a mask; a second insulation film is embedded in the trench and flattened; an upper portion of the first insulation film is selectively removed, and a part of a side face of the second insulation film is exposed; a part of the second insulation film is isotropically removed; a lower portion of the remaining first insulation film is selectively removed; and then a part of the remaining second insulation film is further isotropically removed so that an upper face of the second insulation film is at a predetermined height from a surface of the semiconductor substrate, a taper having a minimum taper angle of 90° or more is formed on the side face of the second insulation film, and a STI is formed.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: January 25, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro Ito, Kunihiro Miyazaki, Kenji Takakura
  • Publication number: 20110001170
    Abstract: A semiconductor device according to the embodiment includes an element region provided with a transistor, a plurality of mixed crystal layers, a drain electrode and a source electrode, an element isolation layer and a dummy pattern. The mixed crystal layers are the layers made of a first atom composing the semiconductor substrate and a second atom having a lattice constant different from the lattice constant of the first atom and formed on both ends of a region, which becomes a channel of the transistor. The dummy pattern is a layer made of the same material as the mixed crystal layers and formed to extend on the surface of the semiconductor substrate and outside of the element region such that a major direction thereof is different from a <110> direction of the semiconductor.
    Type: Application
    Filed: June 24, 2010
    Publication date: January 6, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takayuki Ito, Kunihiro Miyazaki, Kiyotaka Miyano
  • Patent number: 7850818
    Abstract: The disclosure concerns a manufacturing method of a semiconductor device includes dry-etching a semiconductor substrate or a structure formed on the semiconductor substrate; supplying a solution onto the semiconductor substrate; measuring a specific resistance or a conductivity of the supplied solution; and supplying a removal solution for removing the etching residual material onto the semiconductor substrate for a predetermined period of time based on the specific resistance or the conductivity of the solution, when an etching residual material adhering to the semiconductor substrate or the structure is removed.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: December 14, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi Matsumura, Yoshihiro Uozumi, Kunihiro Miyazaki
  • Publication number: 20100151696
    Abstract: A manufacturing method for a semiconductor device, includes, forming an element region on a front surface of a semiconductor substrate, performing a first heat treatment by irradiating first irradiation light having a first irradiation energy density onto the front surface of the semiconductor substrate with a pulse width of 0.1 to 100 msec at the temperature of 1000° C. or less; and performing a second heat treatment by irradiating second irradiation light having a second irradiation energy density onto the surface of the semiconductor substrate with a pulse width of 0.1 to 100 msec at the temperature higher than the temperature in the first heat treatment.
    Type: Application
    Filed: December 10, 2009
    Publication date: June 17, 2010
    Inventors: Takayuki ITO, Masato Fukumoto, Kunihiro Miyazaki
  • Publication number: 20100059180
    Abstract: The disclosure concerns a manufacturing method of a semiconductor device includes dry-etching a semiconductor substrate or a structure formed on the semiconductor substrate; supplying a solution onto the semiconductor substrate; measuring a specific resistance or a conductivity of the supplied solution; and supplying a removal solution for removing the etching residual material onto the semiconductor substrate for a predetermined period of time based on the specific resistance or the conductivity of the solution, when an etching residual material adhering to the semiconductor substrate or the structure is removed.
    Type: Application
    Filed: November 10, 2009
    Publication date: March 11, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi Matsumura, Yoshihiro Uozumi, Kunihiro Miyazaki
  • Patent number: 7635601
    Abstract: The disclosure concerns a manufacturing method of a semiconductor device includes dry-etching a semiconductor substrate or a structure formed on the semiconductor substrate; supplying a solution onto the semiconductor substrate; measuring a specific resistance or a conductivity of the supplied solution; and supplying a removal solution for removing the etching residual material onto the semiconductor substrate for a predetermined period of time based on the specific resistance or the conductivity of the solution, when an etching residual material adhering to the semiconductor substrate or the structure is removed.
    Type: Grant
    Filed: September 14, 2006
    Date of Patent: December 22, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi Matsumura, Yoshihiro Uozumi, Kunihiro Miyazaki
  • Publication number: 20090309133
    Abstract: A manufacturing method for semiconductor device includes: forming an opening, in a surface of a semiconductor substrate being composed of first atom, the opening having an opening ratio y to an area of the surface of the semiconductor substrate ranging from 5 to 30%; forming an epitaxial layer in the opening, the epitaxial layer being made of a mixed crystal containing a second atom in a concentration ranging from 15 to 25%, and the second atom having a lattice constant different from a lattice constant of the first atom; implanting impurity ion into the epitaxial layer; and performing activation annealing at a predetermined temperature T, the predetermined temperature T being equal to or higher than 1150° C. and satisfies a relationship of y?1E-5exp(21541/T).
    Type: Application
    Filed: June 12, 2009
    Publication date: December 17, 2009
    Inventors: Takayuki Ito, Yusuke Oshiki, Kouji Matsuo, Kenichi Yoshino, Takaharu Itani, Takuo Ohashi, Toshihiko Iinuma, Kiyotaka Miyano, Kunihiro Miyazaki
  • Patent number: 7619896
    Abstract: The present invention improves heat dissipation of an electrical junction box. An electrical junction box includes a housing which houses a control circuit board disposed perpendicular to a power distribution board. The control circuit board includes a control circuit constructed on one side of an insulating substrate, electrical components mounted on the control circuit, and a heat dissipating means mounted on the other side. The power distribution board includes a plurality of bus bars laminated via a plurality of insulating layers. Consequently, heat generated by the electrical components can be dissipated efficiently by the heat dissipating means, thereby improving heat dissipation of the electrical junction box.
    Type: Grant
    Filed: July 26, 2005
    Date of Patent: November 17, 2009
    Assignees: Autonetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Hisanobu Yamashita, Kunihiro Miyazaki
  • Publication number: 20090212387
    Abstract: A trench is formed on a semiconductor substrate with a first insulation film patterned on the semiconductor substrate as a mask; a second insulation film is embedded in the trench and flattened; an upper portion of the first insulation film is selectively removed, and a part of a side face of the second insulation film is exposed; a part of the second insulation film is isotropically removed; a lower portion of the remaining first insulation film is selectively removed; and then a part of the remaining second insulation film is further isotropically removed so that an upper face of the second insulation film is at a predetermined height from a surface of the semiconductor substrate, a taper having a minimum taper angle of 90° or more is formed on the side face of the second insulation film, and a STI is formed.
    Type: Application
    Filed: January 26, 2009
    Publication date: August 27, 2009
    Inventors: Yasuhiro Ito, Kunihiro Miyazaki, Kenji Takakura
  • Publication number: 20080310121
    Abstract: The present invention improves heat dissipation of an electrical junction box. An electrical junction box includes a housing which houses a control circuit board disposed perpendicular to a power distribution board. The control circuit board includes a control circuit constructed on one side of an insulating substrate, electrical components mounted on the control circuit, and a heat dissipating means mounted on the other side. The power distribution board includes a plurality of bus bars laminated via a plurality of insulating layers. Consequently, heat generated by the electrical components can be dissipated efficiently by the heat dissipating means, thereby improving heat dissipation of the electrical junction box.
    Type: Application
    Filed: July 26, 2005
    Publication date: December 18, 2008
    Applicants: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hisanobu Yamashita, Kunihiro Miyazaki
  • Patent number: 7439183
    Abstract: A method of manufacturing a semiconductor device. In the method, a thin film is formed on an Si substrate having face orientation (100), that part of the thin film, which lies on an element-isolating region, is removed. Then, the Si substrate is subjected to selective etching, making a trench in the substrate to isolate an element, by using the thin film as mask and a mixture solution of hydrofluoric acid and ozone water.
    Type: Grant
    Filed: August 26, 2005
    Date of Patent: October 21, 2008
    Assignees: Kabushiki Kaisha Toshiba, Seiko Epson Corporation
    Inventors: Kunihiro Miyazaki, Hiroyuki Matsuo, Toshiki Nakajima
  • Publication number: 20080202559
    Abstract: There is disclosed a wafer cleaning method comprising supplying a cleaning water to a wafer cleaned with a chemical solution, measuring the resistivity of a solution including the chemical solution and cleaning water, and differentiating the measured value with respect to time, and cleaning the wafer continuously with the cleaning water until the time differential value of the resistivity becomes equal to or less than a preset value and is held at that values for preset time.
    Type: Application
    Filed: April 16, 2008
    Publication date: August 28, 2008
    Inventors: Kunihiro Miyazaki, Takashi Higuchi, Toshiki Nakajima, Hiroyuki Matsuo
  • Patent number: 7365012
    Abstract: An etching method of subjecting a base material to an etching process using an etching agent containing hydrogen fluoride and ozone is disclosed. The base material has a first region constituted from silicon as a main material and a second region constituted from SiO2 as a main material. The etching method includes the steps of: preparing the base material; and supplying the etching agent onto the base material to form a step between the first and second regions using a feature that an etching rate of silicon by the etching agent is higher than an etching rate of SiO2 by the etching agent, so that the height of the surface of the first region is lower than the height of the surface of the second region.
    Type: Grant
    Filed: August 10, 2005
    Date of Patent: April 29, 2008
    Assignee: Seiko Epson Corporation
    Inventors: Hiroyuki Matsuo, Toshiki Nakajima, Kunihiro Miyazaki
  • Publication number: 20080006295
    Abstract: A processing tank stores heated sulfuric acid, and a semiconductor substrate having resist formed thereon and to be processed is immersed in the heated sulfuric acid. A first introduction unit introduces ozone gas into the sulfuric acid stored in the processing tank. A second introduction unit introduces hydrogen peroxide into the solution containing sulfuric acid and ozone at least before the processing of the semiconductor substrate is completed.
    Type: Application
    Filed: October 4, 2006
    Publication date: January 10, 2008
    Inventors: Kunihiro Miyazaki, Hiroaki Yamada, Hiroshi Tomita, Hajime Onoda
  • Patent number: 7305275
    Abstract: In a small scaled plant intended for flexible manufacturing, a pure water supply system is provided at a low cost without reducing a production efficiency. A pure water system produces a plurality of grades of pure water which are supplied through pipes connected to points of use for cleaning, CMP, lithography, and the like. Upon receipt of a request signal from each point of use for starting to use a certain grade of pure water, a controller determines whether or not a required amount exceeds the capacity of the grade of pure water which can be supplied by the pure water system. If not, the controller sends a use permission signal to the point of use for permitting the same to use the pure water. When a certain use point is using the requested grade of pure water, the controller may not permit the requesting point of use to use the pure water until a use end signal is sent from the use point which is using the pure water.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: December 4, 2007
    Assignee: Ebara Corporation
    Inventors: Kunihiro Miyazaki, Soichi Nadahara, Kinya Usuda, Masaji Akahori, Sota Nakagawa, Ken Nakajima
  • Publication number: 20070233302
    Abstract: A system for controlling production of electronic devices includes a recipe creation unit creating a processing recipe describing processing conditions for first and second processes so as to satisfy a production specification of a characteristic and a yield rate of the electronic devices, and an additional recipe describing additional processing conditions determined based on a relation of the characteristic and the yield rate to a latency time between a completion time of the first process and a start time of the second process so as to satisfy the production specification; and a recipe designation module designating the additional recipe for processing of intermediate products of the electronic devices, produced by the first process, when the latency time exceeds a reference.
    Type: Application
    Filed: November 17, 2006
    Publication date: October 4, 2007
    Inventors: Kunihiro Miyazaki, Yoshihiro Ogawa, Shoichi Harakawa
  • Publication number: 20070178613
    Abstract: The disclosure concerns a manufacturing method of a semiconductor device includes dry-etching a semiconductor substrate or a structure formed on the semiconductor substrate; supplying a solution onto the semiconductor substrate; measuring a specific resistance or a conductivity of the supplied solution; and supplying a removal solution for removing the etching residual material onto the semiconductor substrate for a predetermined period of time based on the specific resistance or the conductivity of the solution, when an etching residual material adhering to the semiconductor substrate or the structure is removed.
    Type: Application
    Filed: September 14, 2006
    Publication date: August 2, 2007
    Inventors: Tsuyoshi Matsumura, Yoshihiro Uozumi, Kunihiro Miyazaki
  • Publication number: 20070095363
    Abstract: A substrate cleaning apparatus, comprises a process tank that holds a mixture containing a hydrogen peroxide solution and sulfuric acid and is used for cleaning a substrate immersed in said mixture; circulation piping that extends between a primary side of said process tank on which said mixture is injected into said process tank and a secondary side of said process tank on which said mixture is discharged from said process tank and has a pump for causing circulation of said mixture; a heater disposed in said circulation piping configured to heat said mixture to a predetermined temperature; a chemical injection pipe configured to inject a hydrogen peroxide solution into said circulation piping at a position between the primary side of said process tank and a secondary side, which is a downstream side, of said heater; and a filter disposed in said circulation piping configured to remove particles in said mixture.
    Type: Application
    Filed: October 27, 2006
    Publication date: May 3, 2007
    Inventors: Hiroshi Tomita, Hiroaki Yamada, Kunihiro Miyazaki, Hajime Onoda