Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.

Abstract: A transistor including a channel layer including an oxide semiconductor material and methods of making the same. The transistor includes a channel layer having a first oxide semiconductor layer having a first oxygen concentration, a second oxide semiconductor layer having a second oxygen concentration and a third oxide semiconductor layer having a third oxygen concentration. The second oxide semiconductor layer is located between the first semiconductor oxide layer and the third oxide semiconductor layer. The second oxygen concentration is lower than the first oxygen concentration and the third oxygen concentration.

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate, the thin film transistor including: a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line, wherein the source line and the bit line each comprise a first conductive material touching the OS layer, and wherein the first conductive material has a work function less than 4.6. The memory cell further includes a dielectric material separating the source line and the bit line.

Abstract: A transistor comprises a colored light shielding layer over the semiconductor layer thereof. The colored light shielding layer reduces exposure of the semiconductor layer to radiation having a wavelength of about 10 nanometers (nm) to about 400 nm. The colored light shielding layer may have a white, black, red, yellow, or gray color. The colored light shielding layer can be formed from a metal oxide film, a p-type oxide semiconductor, or a perovskite. The colored light shielding layer reduces defects that may be generated in the semiconductor layer due to UV light exposure during the manufacturing process, improving device performance and reliability.

Abstract: A device includes a substrate. A first channel region of a first transistor overlies the substrate and a source/drain region is in contact with the first channel region. The source/drain region is adjacent to the first channel region along a first direction, and the source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A dielectric fin structure is adjacent to the source/drain region along a second direction that is transverse to the first direction, and the dielectric fin structure has an upper surface, a lower surface, and an intermediate surface that is disposed between the upper and lower surfaces. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region and on the intermediate surface of the dielectric fin structure.

Abstract: Thermal stability of a transistor is improved in different ways. An interfacial layer between a source/drain electrode and a semiconductor layer is formed from a material having a higher bond dissociation energy than indium oxide. Alternatively, the interfacial layer is formed from a metal-doped oxide semiconductor material. As another option, a metal layer or a metal oxide layer is formed between the source/drain electrode and the interfacial layer.

Abstract: A semiconductor device includes a FEOL structure and a BEOL structure. The BEOL structure is formed over the FEOL structure and includes a barrier dielectric layer, a transistor and a first barrier. The barrier dielectric layer has an upper surface and a lower surface. The transistor is partially formed in the barrier dielectric layer and includes an electrode element, and the electrode element has a first lateral surface, wherein the first lateral surface extends from the upper surface toward the lower surface. The first barrier covers the entirety of the first lateral surface of the electrode element.

Abstract: The present disclosure relates a ferroelectric field-effect transistor (FeFET) device. The FeFET device includes a ferroelectric structure having a first side and a second side. A gate structure is disposed along the first side of the ferroelectric structure, and an oxide semiconductor is disposed along the second side of the ferroelectric structure. The oxide semiconductor has a first semiconductor type. A source region and a drain region are disposed on the oxide semiconductor. The gate structure is laterally between the source region and the drain region. A polarization enhancement structure is arranged on the oxide semiconductor between the source region and the drain region. The polarization enhancement structure includes a semiconductor material or an oxide semiconductor material having a second semiconductor type that is different than the first semiconductor type.

Abstract: A reduced interfacial defect density and low contact resistance can be provided for a thin film transistor by using a compositionally-modulated capping layer. A stack including a gate electrode, a gate dielectric layer, an active layer including a semiconducting metal oxide material, an in-process capping layer including a dielectric metal oxide material can be formed over a substrate. A dielectric material layer can be formed, and a source cavity and a drain cavity can be formed through the dielectric material layer. Exposed portions of the in-process capping layer can be converted into conductive material portions to provide a compositionally-modulated capping layer, which includes a first conductive capping material portion, the second conductive capping material portion, and a dielectric capping material portion.

Abstract: A method of forming a semiconductor structure includes following operations. A memory layer is formed over the first gate electrode. A channel layer is formed over the memory layer. A first SUT treatment is performed. A second dielectric layer is formed over the memory layer and the channel layer. A source electrode and a drain electrode are formed in the second dielectric layer. A temperature of the first SUT treatment is less than approximately 400° C.

Abstract: A field-effect transistor (FET), selectively switchable between first and second states, includes: source and drain regions and a channel region disposed therebetween; a gate arranged to selectively receive a bias voltage which switches the FET between the first and second states; a memory structure between the gate and the channel region, structure including a first portion which is anti-ferroelectric and a second portion which is ferroelectric, both portions being polarized in a first direction when the FET is in the first state; and a depolarization dielectric layer disposed proximate to the memory structure. When the FET is set to the first state, the depolarization dielectric layer destabilizes a polarization of the second portion of the memory structure while maintaining a polarization of the first portion.

Abstract: A method for forming a semiconductor structure includes following operations. A substrate is received. The substrate includes a first dielectric layer and a conducive layer formed in the first dielectric layer. A ferroelectric layer is formed over the first dielectric layer and the conductive layer. A metal oxide semiconductor layer is formed over the ferroelectric layer. An SUT treatment is performed. A temperature of the SUT treatment is less than approximately 400° C.

Abstract: A memory device includes a substrate, word line layers, insulating layers, and memory cells. The word line layers are stacked above the substrate. The insulating layers are stacked above the substrate respectively alternating with the word line layers. The memory cells are distributed along a stacking direction of the word line layers and the insulating layers perpendicularly to a major surface of the substrate. Each memory cell includes a source line electrode and a bit line electrode, a first oxide semiconductor layer, and a second oxide semiconductor layer. The first oxide semiconductor layer is peripherally surrounded by one of the word line layers, the source line electrode, and the bit line electrode. The second oxide semiconductor layer is disposed between the one of the word line layers and the first oxide semiconductor layer.

Abstract: A manufacturing method of a transistor includes at least the following steps. An insulating layer is provided. A source/drain material layer is formed on the insulating layer to cover top surface and sidewalls of the insulating layer. A portion of the source/drain material layer is removed until the insulating layer is exposed, so as to form a source region and a drain region respectively on two opposite sidewalls of the insulating layer. A channel layer is deposited on the insulating layer, the source region, and the drain region. A ferroelectric layer is formed over the channel layer through a non-plasma deposition process. A gate electrode is formed on the ferroelectric layer. The gate electrode, the ferroelectric layer, and the channel layer are patterned to expose at least a portion of the insulating layer, at least a portion of the source region, and at least a portion of the drain region.

Abstract: A transistor device and method of making the same, the transistor device including: a substrate; a word line disposed on the substrate; a gate insulating layer disposed on the word line; a dual-layer semiconductor channel including: a first channel layer disposed on the gate insulating layer; and a second channel layer disposed on the first channel layer, such that the second channel layer contacts side and top surfaces of the first channel layer; and source and drain electrodes electrically coupled to the second channel layer. When a voltage is applied to the word line, the first channel layer has a first electrical resistance and the second channel layer has a second electrical resistance that is different from the first electrical resistance.

Abstract: A semiconductor memory structure includes a gate structure, a ferroelectric layer over the gate structure, a channel layer over the ferroelectric layer, an intervening structure between the ferroelectric layer and the channel layer, and a source structure and a drain structure separated from each other over the channel layer. A thickness of the intervening structure is less than a thickness of the channel layer and less than a thickness of the ferroelectric layer. The channel layer and the intervening structure include different materials.

Abstract: A memory cell includes a ferroelectric (FE) material contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line. The OS layer comprises: a first region adjacent the FE material, the first region having a first concentration of a semiconductor element; a second region adjacent the source line, the second region having a second concentration of the semiconductor element; and a third region between the first region and the second region, the third region having a third concentration of the semiconductor element, the third concentration is greater than the second concentration and less than the first concentration.

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor includes a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line; and a dielectric material separating the source line and the bit line. The dielectric material forms an interface with the OS layer. The dielectric material comprises hydrogen, and a hydrogen concentration at the interface between the dielectric material and the OS layer is no more than 3 atomic percent (at %).

Abstract: A memory device includes a substrate, word line layers, insulating layers, and memory cells. The word line layers are stacked above the substrate. The insulating layers are stacked above the substrate respectively alternating with the word line layers. The memory cells are distributed along a stacking direction of the word line layers and the insulating layers perpendicularly to a major surface of the substrate. Each memory cell includes a source line electrode and a bit line electrode, a first oxide semiconductor layer, and a second oxide semiconductor layer. The first oxide semiconductor layer is peripherally surrounded by one of the word line layers, the source line electrode, and the bit line electrode. The second oxide semiconductor layer is disposed between the one of the word line layers and the first oxide semiconductor layer.

Abstract: A semiconductor device includes a stacked structure, a first flight of steps, a second flight of steps and a third flight of steps. The stacked structure includes a memory array. The first flight of steps, the second flight of steps and the third flight of steps are disposed at a first end of the stacked structure along a first direction. The second flight of steps disposed between the first flight of steps and the third flight of steps, and a length of the second flight of steps is less than a length of the first flight of steps and a length of the third flight of steps along the first direction.