Patents by Inventor Kuo-Chang Chiang
Kuo-Chang Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230369438Abstract: A transistor includes a gate electrode, a gate dielectric layer, a short range order layer, a channel layer, and source/drain regions. The gate dielectric layer is disposed over the gate electrode. The short range order layer is disposed between the gate electrode and the gate dielectric layer. The short ranger order layer has slanted sidewalls. The channel layer is disposed on the gate dielectric layer. The source/drain regions are disposed on the channel layer.Type: ApplicationFiled: May 10, 2022Publication date: November 16, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Neil Quinn Murray, Kuo-Chang Chiang, Mauricio MANFRINI, Tsann Lin
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Publication number: 20230371258Abstract: A memory device includes a multi-layer stack disposed on a substrate and including conductive layers and dielectric layers stacked alternately, a channel layer penetrating through the conductive layers and the dielectric layers, a charge storage layer disposed between the conductive layers and the channel layer, an insulating layer penetrating through the conductive layers and the dielectric layers and disposed between the charge storage layer and the multi-layer stack, and a first conductive pillar and a second conductive pillar enclosed by the channel layer.Type: ApplicationFiled: July 28, 2023Publication date: November 16, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Chang Sun, Yu-Wei Jiang, TsuChing Yang, Kuo-Chang Chiang, Sheng-Chih Lai
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Publication number: 20230363173Abstract: Provided is a method of forming a ferroelectric memory device including: forming a ferroelectric layer between a gate electrode and a channel layer by a first atomic layer deposition (ALD) process. The first ALD process includes: providing a first precursor during a first section; and providing a first mixed precursor during a second section, wherein the first mixed precursor includes a hafnium-containing precursor and a zirconium-containing precursor. In this case, the ferroelectric layer is directly formed as Hf0.5Zr0.5O2 with an orthorhombic phase (O-phase) to enhance the ferroelectric polarization and property.Type: ApplicationFiled: May 9, 2022Publication date: November 9, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Rainer Yen-Chieh Huang, Han-Ting Tsai, Tsann Lin, Kuo-Chang Chiang, Min-Kun Dai, Chung-Te Lin
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Publication number: 20230345731Abstract: A memory device includes a multi-layer stack, a channel layer, a memory material layer and a memory material layer. The multi-layer stack includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately along a first direction. The memory material layer is disposed between the channel layer and each of the conductive layers and the dielectric layers. The conductive pillars extend in the first direction, wherein the at least three conductive pillars are aligned along a second direction substantially perpendicular to the first direction.Type: ApplicationFiled: June 27, 2023Publication date: October 26, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Wei Jiang, Sheng-Chih Lai, TsuChing Yang, Hung-Chang Sun, Kuo-Chang Chiang
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Publication number: 20230337437Abstract: A memory cell includes a thin film transistor over a semiconductor substrate, the thin film transistor including: a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line, wherein the source line and the bit line each comprise a first conductive material touching the OS layer, and wherein the first conductive material has a work function less than 4.6. The memory cell further includes a dielectric material separating the source line and the bit line.Type: ApplicationFiled: June 26, 2023Publication date: October 19, 2023Inventors: Kuo-Chang Chiang, Hung-Chang Sun, Sheng-Chih Lai, TsuChing Yang, Yu-Wei Jiang
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Publication number: 20230327024Abstract: A transistor including a channel layer including an oxide semiconductor material and methods of making the same. The transistor includes a channel layer having a first oxide semiconductor layer having a first oxygen concentration, a second oxide semiconductor layer having a second oxygen concentration and a third oxide semiconductor layer having a third oxygen concentration. The second oxide semiconductor layer is located between the first semiconductor oxide layer and the third oxide semiconductor layer. The second oxygen concentration is lower than the first oxygen concentration and the third oxygen concentration.Type: ApplicationFiled: June 14, 2023Publication date: October 12, 2023Inventors: Kuo-Chang Chiang, Hung-Chang Sun, Sheng-Chih Lai, TsuChing Yang, Yu-Wei Jiang, Feng-Cheng Yang, Neil Quinn Murray
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Publication number: 20230328980Abstract: A memory device includes a stack of gate electrode layers and interconnect layers arranged over a substrate. A first memory cell that is arranged over the substrate includes a first source/drain conductive lines and a second source/drain conductive line extending vertically through the stack of gate electrode layers. A channel layer and a memory layer are arranged on outer sidewalls of the first and second source/drain conductive lines. A first barrier structure is arranged between the first and second source/drain conductive lines. A first protective liner layer separates the first barrier structure from each of the first and second source/drain conductive lines. A second barrier structure is arranged on an opposite side of the first source/drain conductive line and is spaced apart from the first source/drain conductive line by a second protective liner layer.Type: ApplicationFiled: June 16, 2023Publication date: October 12, 2023Inventors: Tsu Ching Yang, Sheng-Chih Lai, Yu-Wei Jiang, Kuo-Chang Chiang, Hung-Chang Sun, Chen-Jun Wu, Feng-Cheng Yang, Chung-Te Lin
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Publication number: 20230328996Abstract: In some embodiments, the present disclosure relates to a method for forming a memory device, including forming a plurality of word line stacks respectively including a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate, forming a data storage layer along opposing sidewalls of the word line stacks, forming a channel layer along opposing sidewalls of the data storage layer, forming an inner insulating layer between inner sidewalls of the channel layer and including a first dielectric material, performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening, forming an isolation structure filling the isolation opening and including a second dielectric material, performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings, and forming source/drain contacts in the source/drainType: ApplicationFiled: June 14, 2023Publication date: October 12, 2023Inventors: Tsu Ching Yang, Feng-Cheng Yang, Sheng-Chih Lai, Yu-Wei Jiang, Kuo-Chang Chiang, Hung-Chang Sun, Chen-Jun Wu, Chung-Te Lin
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Publication number: 20230317848Abstract: A memory cell includes a ferroelectric (FE) material contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line. The OS layer comprises: a first region adjacent the FE material, the first region having a first concentration of a semiconductor element; a second region adjacent the source line, the second region having a second concentration of the semiconductor element; and a third region between the first region and the second region, the third region having a third concentration of the semiconductor element, the third concentration is greater than the second concentration and less than the first concentration.Type: ApplicationFiled: June 7, 2023Publication date: October 5, 2023Inventors: Kuo-Chang Chiang, Hung-Chang Sun, Sheng-Chih Lai, TsuChing Yang, Yu-Wei Jiang
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Patent number: 11729988Abstract: A memory device includes a multi-layer stack, a channel layer, a memory material layer and at least three conductive pillars. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. The memory material layer is disposed between the channel layer and each of the plurality of conductive layers and the plurality of dielectric layers. The conductive pillars are surrounded by the channel layer and the memory material layer, wherein the at least three conductive pillars are electrically connected to conductive lines respectively.Type: GrantFiled: January 27, 2021Date of Patent: August 15, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Wei Jiang, Sheng-Chih Lai, Tsuching Yang, Hung-Chang Sun, Kuo-Chang Chiang
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Patent number: 11729987Abstract: A memory cell includes a thin film transistor over a semiconductor substrate, the thin film transistor including: a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line, wherein the source line and the bit line each comprise a first conductive material touching the OS layer, and wherein the first conductive material has a work function less than 4.6. The memory cell further includes a dielectric material separating the source line and the bit line.Type: GrantFiled: December 11, 2020Date of Patent: August 15, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Chang Chiang, Hung-Chang Sun, Sheng-Chih Lai, TsuChing Yang, Yu-Wei Jiang
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Publication number: 20230253464Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor includes a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line; and a dielectric material separating the source line and the bit line. The dielectric material forms an interface with the OS layer. The dielectric material comprises hydrogen, and a hydrogen concentration at the interface between the dielectric material and the OS layer is no more than 3 atomic percent (at %).Type: ApplicationFiled: April 14, 2023Publication date: August 10, 2023Inventors: Kuo-Chang Chiang, Hung-Chang Sun, Sheng-Chih Lai, TsuChing Yang, Yu-Wei Jiang
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Patent number: 11723199Abstract: A memory device includes a stack of gate electrode layers and interconnect layers arranged over a substrate. A first memory cell that is arranged over the substrate includes a first source/drain conductive lines and a second source/drain conductive line extending vertically through the stack of gate electrode layers. A channel layer and a memory layer are arranged on outer sidewalls of the first and second source/drain conductive lines. A first barrier structure is arranged between the first and second source/drain conductive lines. A first protective liner layer separates the first barrier structure from each of the first and second source/drain conductive lines. A second barrier structure is arranged on an opposite side of the first source/drain conductive line and is spaced apart from the first source/drain conductive line by a second protective liner layer.Type: GrantFiled: March 3, 2021Date of Patent: August 8, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsu Ching Yang, Sheng-Chih Lai, Yu-Wei Jiang, Kuo-Chang Chiang, Hung-Chang Sun, Chen-Jun Wu, Feng-Cheng Yang, Chung-Te Lin
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Patent number: 11723210Abstract: In some embodiments, the present disclosure relates to a method for forming a memory device, including forming a plurality of word line stacks respectively including a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate, forming a data storage layer along opposing sidewalls of the word line stacks, forming a channel layer along opposing sidewalls of the data storage layer, forming an inner insulating layer between inner sidewalls of the channel layer and including a first dielectric material, performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening, forming an isolation structure filling the isolation opening and including a second dielectric material, performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings, and forming source/drain contacts in the source/drainType: GrantFiled: May 28, 2021Date of Patent: August 8, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsu Ching Yang, Feng-Cheng Yang, Sheng-Chih Lai, Yu-Wei Jiang, Kuo-Chang Chiang, Hung-Chang Sun, Chen-Jun Wu, Chung-Te Lin
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Publication number: 20230238462Abstract: A transistor device and method of making the same, the transistor device including: a substrate; a word line disposed on the substrate; a gate insulating layer disposed on the word line; a dual-layer semiconductor channel including: a first channel layer disposed on the gate insulating layer; and a second channel layer disposed on the first channel layer, such that the second channel layer contacts side and top surfaces of the first channel layer; and source and drain electrodes electrically coupled to the second channel layer. When a voltage is applied to the word line, the first channel layer has a first electrical resistance and the second channel layer has a second electrical resistance that is different from the first electrical resistance.Type: ApplicationFiled: March 28, 2023Publication date: July 27, 2023Inventors: Hung Wei LI, Yu-Ming LIN, Mauricio MANFRINI, Kuo-Chang CHIANG, Sai-Hooi YEONG
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Patent number: 11710790Abstract: A memory cell includes a ferroelectric (FE) material contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line. The OS layer comprises: a first region adjacent the FE material, the first region having a first concentration of a semiconductor element; a second region adjacent the source line, the second region having a second concentration of the semiconductor element; and a third region between the first region and the second region, the third region having a third concentration of the semiconductor element, the third concentration is greater than the second concentration and less than the first concentration.Type: GrantFiled: January 15, 2021Date of Patent: July 25, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Chang Chiang, Hung-Chang Sun, Sheng-Chih Lai, TsuChing Yang, Yu-Wei Jiang
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Patent number: 11696448Abstract: A device includes a dielectric layer, a conductive layer, electrode layers and an oxide semiconductor layer. The dielectric layer has a first surface and a second surface opposite to the first surface. The conductive layer is disposed on the first surface of the dielectric layer. The electrode layers are disposed on the second surface of the dielectric layer. The oxide semiconductor layer is disposed in between the second surface of the dielectric layer and the electrode layers, wherein the oxide semiconductor layer comprises a material represented by formula 1 (InxSnyTizMmOn). In formula 1, 0<x<1, 0?y<1, 0<z<1, 0<m<1, 0<n<1, and M represents at least one metal.Type: GrantFiled: April 20, 2021Date of Patent: July 4, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Chang Sun, Sheng-Chih Lai, TsuChing Yang, Yu-Wei Jiang, Kuo-Chang Chiang
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Patent number: 11646379Abstract: A transistor device and method of making the same, the transistor device including: a substrate; a word line disposed on the substrate; a gate insulating layer disposed on the word line; a dual-layer semiconductor channel including: a first channel layer disposed on the gate insulating layer; and a second channel layer disposed on the first channel layer, such that the second channel layer contacts side and top surfaces of the first channel layer; and source and drain electrodes electrically coupled to the second channel layer. When a voltage is applied to the word line, the first channel layer has a first electrical resistance and the second channel layer has a second electrical resistance that is different from the first electrical resistance.Type: GrantFiled: April 12, 2021Date of Patent: May 9, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hung Wei Li, Kuo-Chang Chiang, Mauricio Manfrini, Sai-Hooi Yeong, Yu-Ming Lin
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Patent number: 11640974Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor includes a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line; and a dielectric material separating the source line and the bit line. The dielectric material forms an interface with the OS layer. The dielectric material comprises hydrogen, and a hydrogen concentration at the interface between the dielectric material and the OS layer is no more than 3 atomic percent (at %).Type: GrantFiled: December 11, 2020Date of Patent: May 2, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Chang Chiang, Hung-Chang Sun, Sheng-Chih Lai, Tsuching Yang, Yu-Wei Jiang
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Publication number: 20230120530Abstract: A memory device includes a stacked structure including a plurality of memory cells, and first and second flights of steps. The first flights of steps are disposed at an end of the stacked structure along the first direction. The second flights of steps are adjacent to the first flights of steps disposed at the end of the stacked structure along the first direction. The first flights of steps and the second flights of steps comprise first portions and second portions alternately disposed along the first direction. The second portions are wider than the first portions along the second direction.Type: ApplicationFiled: December 21, 2022Publication date: April 20, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: TsuChing Yang, Hung-Chang Sun, Sheng-Chih Lai, Yu-Wei Jiang, Kuo-Chang Chiang