Patents by Inventor Kuo-Cheng Ching

Kuo-Cheng Ching has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20210265485
    Abstract: A semiconductor device includes a substrate, a first dielectric fin, a semiconductor fin, a metal gate structure, an epitaxy structure, and a contact etch stop layer. The first dielectric fin is disposed over the substrate. The semiconductor fin is disposed over the substrate, in which along a lengthwise direction of the first dielectric fin and the semiconductor fin, the first dielectric fin is in contact with a first sidewall of the semiconductor fin. The metal gate structure crosses the first dielectric fin and the semiconductor fin. The epitaxy structure is over and in contact with the semiconductor fin. The contact etch stop layer is over and in contact with first dielectric fin.
    Type: Application
    Filed: May 7, 2021
    Publication date: August 26, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng CHING, Shi-Ning JU, Kuan-Ting PAN, Kuan-Lun CHENG, Chih-Hao WANG
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20210265464
    Abstract: A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the first channel layers, a gate electrode layer disposed on the gate dielectric layer and wrapping each of the first channel layers, and a liner semiconductor layer disposed between the first channel layers and the first source/drain region.
    Type: Application
    Filed: May 10, 2021
    Publication date: August 26, 2021
    Inventors: Ka-Hing FUNG, Kuo-Cheng CHING, Ying-Keung LEUNG
  • SEMICONDUCTOR DEVICE AND FABRICATING THE SAME
    Publication number: 20210265343
    Abstract: An integrated circuit (IC) device comprises a substrate having a metal-oxide-semiconductor (MOS) region; a gate region disposed over the substrate and in the MOS region; and source/drain features in the MOS region and separated by the gate region. The gate region includes a fin structure and a nanowire over the fin structure. The nanowire extends from the source feature to the drain feature.
    Type: Application
    Filed: May 10, 2021
    Publication date: August 26, 2021
    Inventors: Kuo-Cheng Ching, Ting-Hung Hsu
  • SEMICONDUCTOR DEVICE STRUCTURE
    Publication number: 20210234036
    Abstract: A semiconductor device structure includes a fin structure, a semiconductive capping layer, an oxide layer, and a gate structure. The fin structure protrudes above a substrate. The semiconductive capping layer wraps around three sides of a channel region of the fin structure. The oxide layer wraps around three sides of the semiconductive capping layer. A thickness of a top portion of the semiconductive capping layer is less than a thickness of a top portion of the oxide layer. The gate structure wraps around three sides of the oxide layer.
    Type: Application
    Filed: April 17, 2021
    Publication date: July 29, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng CHING, Kuan-Ting PAN, Kuan-Lun CHENG, Chih-Hao WANG
  • SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20210226036
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an isolation structure formed over a substrate, and a first stacked nanostructure and a second stacked nanostructure extending above the isolation structure. The semiconductor device structure includes an inner spacer layer surrounding the first stacked nanostructure, and a dummy fin structure formed over the isolation structure. The dummy fin structure is between the first stacked nanostructure and the second stacked nanostructure, and a capping layer formed over the dummy fin structure. The inner spacer layer is in direct contact with the dummy fin structure and the capping layer.
    Type: Application
    Filed: April 1, 2021
    Publication date: July 22, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng CHING, Zhi-Chang LIN, Kuan-Ting PAN, Chih-Hao WANG, Shi-Ning JU
  • Dummy Dielectric Fin Design for Parasitic Capacitance Reduction
    Publication number: 20210226037
    Abstract: A semiconductor device includes a first device fin and a second device fin. A first source/drain component is epitaxially grown over the first device fin. A second source/drain component is epitaxially grown over the second device fin. A first dummy fin structure is disposed between the first device fin and the second device fin. A gate structure partially wraps around the first device fin, the second device fin, and the first dummy fin structure. A first portion of the first dummy fin structure is disposed between the first source/drain component and the second source/drain component and outside the gate structure. A second portion of the first dummy fin structure is disposed underneath the gate structure. The first portion of the first dummy fin structure and the second portion of the first dummy fin structure have different physical characteristics.
    Type: Application
    Filed: April 5, 2021
    Publication date: July 22, 2021
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Shi Ning Ju, Kuan-Lun Cheng
  • Reducing parasitic capacitance for gate-all-around device by forming extra inner spacers
    Patent number: 11069793
    Abstract: A semiconductor device includes a plurality of nanostructures. The nanostructures each contain a semiconductive material. A plurality of first spacers circumferentially wrap around the nanostructures. A plurality of second spacers circumferentially wrap around the first spacers. A plurality of third spacers is disposed between the second spacers vertically. A gate structure surrounds the second spacers and the third spacers.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: July 20, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Shi Ning Ju, Kuan-Lun Cheng
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20210202715
    Abstract: A semiconductor device includes a substrate, a first semiconductor fin, a second semiconductor fin, a gate structure, a plurality of source/drain structures, a shallow trench isolation (STI) oxide, and a dielectric layer. The first semiconductor fin extends upwardly from the substrate. The second semiconductor fin extends upwardly from the substrate. The gate structure extends across the first and second semiconductor fins. The source/drain structures are on the first and second semiconductor fins. The STI oxide extends continuously between the first and second semiconductor fins and has a U-shaped profile when viewed in a cross section taken along a lengthwise direction of the gate structure. The dielectric layer is partially embedded in the STI oxide and has a U-shaped profile when viewed in the cross section taken along the lengthwise direction of the gate structure.
    Type: Application
    Filed: March 12, 2021
    Publication date: July 1, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng CHING, Kuan-Lun CHENG, Chih-Hao WANG, Keng-Chu LIN, Shi-Ning JU
  • Fin-Like Field Effect Transistor Patterning Methods For Achieving Fin Width Uniformity
    Publication number: 20210184015
    Abstract: FinFET patterning methods are disclosed for achieving fin width uniformity. An exemplary method includes forming a mandrel layer over a substrate. A first cut removes a portion of the mandrel layer, leaving a mandrel feature disposed directly adjacent to a dummy mandrel feature. The substrate is etched using the mandrel feature and the dummy mandrel feature as an etch mask, forming a dummy fin feature and an active fin feature separated by a first spacing along a first direction. A second cut removes a portion of the dummy fin feature and a portion of the active fin feature, forming dummy fins separated by a second spacing and active fins separated by the second spacing. The second spacing is along a second direction substantially perpendicular to the first direction. A third cut removes the dummy fins, forming fin openings, which are filled with a dielectric material to form dielectric fins.
    Type: Application
    Filed: February 9, 2021
    Publication date: June 17, 2021
    Inventors: Kuo-Cheng Ching, Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang
  • Semiconductor arrangement with one or more semiconductor columns
    Patent number: 11038052
    Abstract: A semiconductor arrangement comprises a substrate region and a first semiconductor column projecting from the substrate region. The semiconductor arrangement comprises a second semiconductor column projecting from the substrate region. The second semiconductor column is separated a first distance from the first semiconductor column. The first distance is between about 10 nm to about 30 nm.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: June 15, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Jean-Pierre Colinge, Kuo-Cheng Ching, Ta-Pen Guo, Carlos H. Diaz
  • Fin-Like Field Effect Transistor Patterning Methods For Achieving Fin Width Uniformity
    Publication number: 20210175341
    Abstract: FinFET patterning methods are disclosed for achieving fin width uniformity. An exemplary method includes forming a mandrel layer over a substrate. A first cut removes a portion of the mandrel layer, leaving a mandrel feature disposed directly adjacent to a dummy mandrel feature. The substrate is etched using the mandrel feature and the dummy mandrel feature as an etch mask, forming a dummy fin feature and an active fin feature separated by a first spacing along a first direction. A second cut removes a portion of the dummy fin feature and a portion of the active fin feature, forming dummy fins separated by a second spacing and active fins separated by the second spacing. The second spacing is along a second direction substantially perpendicular to the first direction. A third cut removes the dummy fins, forming fin openings, which are filled with a dielectric material to form dielectric fins.
    Type: Application
    Filed: February 17, 2021
    Publication date: June 10, 2021
    Inventors: Kuo-Cheng Ching, Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang
  • Semiconductor arrangement and method of manufacture
    Patent number: 11024545
    Abstract: A method for forming a semiconductor arrangement comprises forming a first fin in a semiconductor layer. A first gate dielectric layer includes a first high-k material is formed over the first fin. A first sacrificial gate electrode is formed over the first fin. A dielectric layer is formed adjacent the first sacrificial gate electrode and over the first fin. The first sacrificial gate electrode is removed to define a first gate cavity in the dielectric layer. A second gate dielectric layer including a second dielectric material different than the first high-k material is formed over the first gate dielectric layer in the first gate cavity. A first gate electrode is formed in the first gate cavity over the second gate dielectric layer.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: June 1, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Kuo-Cheng Ching, Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu
  • Fill Fins for Semiconductor Devices
    Publication number: 20210151560
    Abstract: A semiconductor device includes a substrate, an isolation feature over the substrate, a first device fin protruding from the substrate and through the isolation feature, and a second device fin protruding from the substrate and through the isolation feature. The semiconductor device also includes a dielectric fin disposed between the first and second device fins and a metal gate stack engaging the first and second device fins. The dielectric fin separates the metal gate stack into first and second segments and provides electrical isolation between the first and second segments. A portion of the isolation feature is directly under a bottom surface of the dielectric fin.
    Type: Application
    Filed: December 28, 2020
    Publication date: May 20, 2021
    Inventors: Kuo-Cheng Ching, Kuan-Lun Cheng, Chih-Hao Wang
  • System and method for widening fin widths for small pitch FinFET devices
    Patent number: 11011427
    Abstract: A semiconductor layer is etched into a plurality of fin structures. A first nitridation process is performed to side surfaces of the fin structures. The first nitridation process forms a first oxynitride layer at the side surfaces of the fin structures. A liner oxide layer is formed on the first oxynitride layer. An isolation structure is formed around the fin structures after the forming of the liner oxide layer.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Shi Ning Ju, Chih-Hao Wang, Ying-Keung Leung, Carlos H. Diaz
  • Semiconductor device structure and method for forming the same
    Patent number: 11004959
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an isolation structure formed over a substrate, and a first stacked wire structure and a second stacked wire structure extending above the isolation structure. The semiconductor device structure includes a dummy fin structure formed over the isolation structure, and the dummy fin structure is between the first stacked wire structure and the second stacked wire structure. The semiconductor device structure also includes a capping layer formed over the dummy fin structure. The isolation structure has a first width, the dummy fin structure has a second width, and the second width is smaller than the first width.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Zhi-Chang Lin, Kuan-Ting Pan, Chih-Hao Wang, Shi-Ning Ju
  • Semiconductor device and fabricating the same
    Patent number: 11004847
    Abstract: An integrated circuit (IC) device comprises a substrate having a metal-oxide-semiconductor (MOS) region; a gate region disposed over the substrate and in the MOS region; and source/drain features in the MOS region and separated by the gate region. The gate region includes a fin structure and a nanowire over the fin structure. The nanowire extends from the source feature to the drain feature.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: May 11, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Ting-Hung Hsu
  • Semiconductor device and manufacturing method thereof
    Patent number: 11004960
    Abstract: A semiconductor device includes a substrate, a first dielectric fin, a second dielectric fin, a semiconductor fin, an epitaxy structure, and a metal gate structure. The first dielectric fin and the second dielectric fin disposed over the substrate. The semiconductor fin is disposed over the substrate, in which the semiconductor fin is between the first dielectric fin and the second dielectric fin. The epitaxy structure covers at least two surfaces of the semiconductor fin, in which the epitaxy structure is in contact with the first dielectric fin and is separated from the second dielectric fin. The metal gate structure crosses the first dielectric fin, the second dielectric fin, and the semiconductor fin.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: May 11, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Shi-Ning Ju, Kuan-Ting Pan, Kuan-Lun Cheng, Chih-Hao Wang
  • Semiconductor device including a liner layer between a channel and a source/drain epitaxial layer
    Patent number: 11004934
    Abstract: A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the first channel layers, a gate electrode layer disposed on the gate dielectric layer and wrapping each of the first channel layers, and a liner semiconductor layer disposed between the first channel layers and the first source/drain region.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: May 11, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ka-Hing Fung, Kuo-Cheng Ching, Ying-Keung Leung
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20210134798
    Abstract: In a method of manufacturing a semiconductor device, a separation wall made of a dielectric material is formed between two fin structures. A dummy gate structure is formed over the separation wall and the two fin structures. An interlayer dielectric (ILD) layer is formed over the dummy gate structure. An upper portion of the ILD layer is removed, thereby exposing the dummy gate structure. The dummy gate structure is replaced with a metal gate structure. A planarization operation is performed to expose the separation wall, thereby dividing the metal gate structure into a first gate structure and a second gate structure. The first gate structure and the second gate structure are separated by the separation wall.
    Type: Application
    Filed: December 14, 2020
    Publication date: May 6, 2021
    Inventors: Kuo-Cheng CHING, Chih-Hao WANG, Chih-Liang CHEN, Shi Ning JU
  • Integrated circuits with buried interconnect conductors
    Patent number: 10998238
    Abstract: Examples of an integrated circuit with an interconnect structure that includes a buried interconnect conductor and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a substrate that includes a plurality of fins extending from a remainder of the substrate. A spacer layer is formed between the plurality of fins, and a buried interconnect conductor is formed on the spacer layer between the plurality of fins. A set of capping layers is formed on the buried interconnect conductor between the plurality of fins. A contact recess is etched through the set of capping layers that exposes the buried interconnect conductor, and a contact is formed in the contact recess that is electrically coupled to the buried interconnect conductor.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang