Patents by Inventor Kuo-Cheng Ching

Kuo-Cheng Ching has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10410930
    Abstract: Various methods are disclosed herein for fabricating non-planar circuit devices having strain-producing features. An exemplary method includes forming a fin structure that includes a first portion that includes a first semiconductor material and a second portion that includes a second semiconductor material that is different than the first semiconductor material. The method further includes forming a masking layer over a source region and a drain region of the fin structure, forming a strain-producing feature over the first portion of the fin structure in a channel region, removing the masking layer and forming an isolation feature over the strain-producing feature, forming an epitaxial feature over the second portion of the fin structure in the source region and the drain region, and performing a gate replacement process to form a gate structure over the second portion of the fin structure in the channel region.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: September 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Ka-Hing Fung, Zhiqiang Wu
  • Patent number: 10403714
    Abstract: A semiconductor device includes a semiconductor substrate, first and second device fins extending from the semiconductor substrate, and a fill fin disposed on the semiconductor substrate and between the first and second device fins, wherein the fill fin has an opening. The semiconductor device further includes a first gate structure extending continuously from a channel region of the first device fin to a channel region of the second device fin through the opening.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: September 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 10403545
    Abstract: The present disclosure describes a method to reduce power consumption in a fin structure. For example, the method includes forming a first and a second semiconductor fins on a substrate with different heights. The method also includes forming insulating fins between and adjacent to the first and the second semiconductor fins. Further, the method includes forming a first and second epitaxial stacks with different heights on each of the first and second semiconductor fins.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: September 3, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Kuan-Lun Cheng
  • Publication number: 20190267488
    Abstract: A semiconductor arrangement comprises a substrate region and a first semiconductor column projecting from the substrate region. The semiconductor arrangement comprises a second semiconductor column projecting from the substrate region. The second semiconductor column is separated a first distance from the first semiconductor column. The first distance is between about 10 nm to about 30 nm.
    Type: Application
    Filed: May 13, 2019
    Publication date: August 29, 2019
    Inventors: Jean-Pierre Colinge, Kuo-Cheng Ching, Ta-Pen Guo, Carlos H. Diaz
  • Publication number: 20190267375
    Abstract: Various examples of a buried interconnect line are disclosed herein. In an example, a device includes a fin disposed on a substrate. The fin includes an active device. A plurality of isolation features are disposed on the substrate and below the active device. An interconnect is disposed on the substrate and between the plurality of isolation features such that the interconnect is below a topmost surface of the plurality of isolation features. The interconnect is electrically coupled to the active device. In some such examples, a gate stack of the active device is disposed over a channel region of the active device and is electrically coupled to the interconnect. In some such examples, a source/drain contact is electrically coupled to a source/drain region of the active device, and the source/drain contact is electrically coupled to the interconnect.
    Type: Application
    Filed: May 9, 2019
    Publication date: August 29, 2019
    Inventors: Kuo-Cheng Ching, Shi Ning Ju, Kuan-Ting Pan, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20190259757
    Abstract: The present disclosure provides a method for fabricating an integrated circuit device. The method includes providing a precursor including a substrate having first and second metal-oxide-semiconductor (MOS) regions. The first and second MOS regions include first and second gate regions, semiconductor layer stacks, and source/drain regions respectively. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the first gate region to form first outer oxide layer and inner nanowire set, and exposing the first inner nanowire set. A first high-k/metal gate (HK/MG) stack wraps around the first inner nanowire set. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the second gate region to form second outer oxide layer and inner nanowire set, and exposing the second inner nanowire set. A second HK/MG stack wraps around the second inner nanowire set.
    Type: Application
    Filed: May 6, 2019
    Publication date: August 22, 2019
    Inventors: Kuo-Cheng Ching, Ting-Hung Hsu
  • Publication number: 20190237572
    Abstract: A device includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate. A semiconductor fin is between opposite portions of the isolation regions, wherein the semiconductor fin is over top surfaces of the isolation regions. A gate stack overlaps the semiconductor fin. A source/drain region is on a side of the gate stack and connected to the semiconductor fin. The source/drain region includes an inner portion thinner than the semiconductor fin, and an outer portion outside the inner portion. The semiconductor fin and the inner portion of the source/drain region have a same composition of group IV semiconductors.
    Type: Application
    Filed: April 5, 2019
    Publication date: August 1, 2019
    Inventors: Kuo-Cheng Ching, Ka-Hing Fung, Zhiqiang Wu
  • Publication number: 20190237464
    Abstract: Devices and methods of forming a FET including a substrate having a first fin and a second fin extending therefrom. A high-k gate dielectric layer and a ferroelectric insulator layer are deposited over the first fin and the second fin. In some embodiments, a dummy gate layer is deposited over the ferroelectric insulator layer over the first fin and the second fin to form a first gate stack over the first fin and a second gate stack over the second fin. The dummy gate layer of the first gate stack is then removed (while maintaining the ferroelectric insulator layer) to form a first trench. And the dummy gate layer and the ferroelectric insulator layer of the second gate stack are removed to form a second trench. At least one metal gate layer is formed in the first trench and the second trench.
    Type: Application
    Filed: April 10, 2019
    Publication date: August 1, 2019
    Inventors: Kuo-Cheng CHING, Kuan-Lun CHENG, Chih-Hao WANG, Sai-Hooi YEONG, Tzer-Min SHEN, Chi-Hsing HSU
  • Publication number: 20190229120
    Abstract: In a method of manufacturing a semiconductor device, a separation wall made of a dielectric material is formed between two fin structures. A dummy gate structure is formed over the separation wall and the two fin structures. An interlayer dielectric (ILD) layer is formed over the dummy gate structure. An upper portion of the ILD layer is removed, thereby exposing the dummy gate structure. The dummy gate structure is replaced with a metal gate structure. A planarization operation is performed to expose the separation wall, thereby dividing the metal gate structure into a first gate structure and a second gate structure. The first gate structure and the second gate structure are separated by the separation wall.
    Type: Application
    Filed: March 29, 2019
    Publication date: July 25, 2019
    Inventors: Kuo-Cheng CHING, Chih-Hao WANG, Chih-Liang CHEN, Shi Ning JU
  • Patent number: 10361220
    Abstract: A method for fabricating a semiconductor device having a substantially undoped channel region includes performing an ion implantation into a substrate, depositing a first epitaxial layer over the substrate, and depositing a second epitaxial layer over the first epitaxial layer. In various examples, a plurality of fins is formed extending from the substrate. Each of the plurality of fins includes a portion of the ion implanted substrate, a portion of the first epitaxial layer, and a portion of the second epitaxial layer. In some embodiments, the portion of the second epitaxial layer of each of the plurality of fins includes an undoped channel region. In various embodiments, the portion of the first epitaxial layer of each of the plurality of fins is oxidized.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: July 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Wang, Ching-Wei Tsai, Kuo-Cheng Ching, Jhon Jhy Liaw, Wai-Yi Lien
  • Patent number: 10361270
    Abstract: A nanowire field effect transistor (FET) device and method for forming a nanowire FET device are provided. A nanowire FET including a source region and a drain region is formed. The nanowire FET further includes a nanowire that connects the source region and the drain region. A source silicide is formed on the source region, and a drain silicide is formed on the drain region. The source silicide is comprised of a first material that is different from a second material comprising the drain silicide.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: July 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jean-Pierre Colinge, Cheng-Tung Lin, Kuo-Cheng Ching, Carlos H. Diaz
  • Patent number: 10361280
    Abstract: A method of forming a fin field effect transistors (finFET) on a substrate includes forming a fin structure on the substrate, forming a protective layer on the fin structure, and forming a polysilicon structure on the protective layer. The method further includes modifying the polysilicon structure such that a first horizontal dimension of a first portion of the modified polysilicon structure is smaller than a second horizontal dimension of a second portion of the modified polysilicon structure. The method further includes replacing the modified polysilicon structure with a gate structure having a first horizontal dimension of a first portion of the gate structure that is smaller than a second horizontal dimension of a second portion of the gate structure.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: July 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Ching-Wei Tsai, Kuan-Lun Cheng
  • Patent number: 10361126
    Abstract: A semiconductor layer is etched into a plurality of fin structures. A first nitridation process is performed to side surfaces of the fin structures. The first nitridation process forms a first oxynitride layer at the side surfaces of the fin structures. A liner oxide layer is formed on the first oxynitride layer. An isolation structure is formed around the fin structures after the forming of the liner oxide layer.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: July 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Shi Ning Ju, Chih-Hao Wang, Ying-Keung Leung, Carlos H. Diaz
  • Patent number: 10355137
    Abstract: A device includes isolation regions extending into a semiconductor substrate, with a substrate strip between opposite portions of the isolation regions having a first width. A source/drain region has a portion overlapping the substrate strip, wherein an upper portion of the source/drain region has a second width greater than the first width. The upper portion of the source/drain region has substantially vertical sidewalls. A source/drain silicide region has inner sidewalls contacting the vertical sidewalls of the source/drain region.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Chi-Wen Liu, Chih-Hao Wang, Ying-Keung Leung
  • Patent number: 10347751
    Abstract: Semiconductor structures including active fin structures, dummy fin structures, epitaxy layers, a Ge containing oxide layer and methods of manufacture thereof are described. By implementing the Ge containing oxide layer on the surface of the epitaxy layers formed on the source/drain regions of some of the FinFET devices, a self-aligned epitaxy process is enabled. By implementing dummy fin structures and a self-aligned etch, both the epitaxy layers and metal gate structures from adjacent FinFET devices are isolated in a self-aligned manner.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: July 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Kuan-Lun Cheng
  • Patent number: 10340191
    Abstract: A method of forming a fin structure of a semiconductor device, such as a fin field effect transistor (FinFET) is provided. In an embodiment, trenches are formed in a substrate, and a liner is formed along sidewalls of the trenches, wherein a region between adjacent trenches define a fin. A dielectric material is formed in the trenches. Portions of the semiconductor material of the fin are replaced with a second semiconductor material and a third semiconductor material, the second semiconductor material having a different lattice constant than the substrate and the third semiconductor material having a different lattice constant than the second semiconductor material. Portions of the second semiconductor material are oxidized.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Jiun-Jia Huang, Chao-Hsiung Wang, Chi-Wen Liu
  • Patent number: 10325989
    Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a first silicide region on a first type surface region of the first type region. The first silicide region is separated at least one of a first distance from a first type diffusion region of the first type region or a second distance from the channel region.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: June 18, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jean-Pierre Colinge, Kuo-Cheng Ching, Ta-Pen Guo, Carlos H. Diaz
  • Patent number: 10325816
    Abstract: The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a substrate having a first gate region, a first fin structure over the substrate in the first gate region. The first fin structure includes an upper semiconductor material member, a lower semiconductor material member, surrounded by an oxide feature and a liner wrapping around the oxide feature of the lower semiconductor material member, and extending upwards to wrap around a lower portion of the upper semiconductor material member. The device also includes a dielectric layer laterally proximate to an upper portion of the upper semiconductor material member. Therefore the upper semiconductor material member includes a middle portion that is neither laterally proximate to the dielectric layer nor wrapped by the liner.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: June 18, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Ka-Hing Fung, Chih-Sheng Chang, Zhiqiang Wu
  • Publication number: 20190172926
    Abstract: A method of forming a fin field effect transistors (finFET) on a substrate includes forming a fin structure on the substrate, forming a protective layer on the fin structure, and forming a polysilicon structure on the protective layer. The method further includes modifying the polysilicon structure such that a first horizontal dimension of a first portion of the modified polysilicon structure is smaller than a second horizontal dimension of a second portion of the modified polysilicon structure. The method further includes replacing the modified polysilicon structure with a gate structure having a first horizontal dimension of a first portion of the gate structure that is smaller than a second horizontal dimension of a second portion of the gate structure.
    Type: Application
    Filed: November 29, 2018
    Publication date: June 6, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng CHING, Chih-Hao WANG, Ching-Wei TSAI, Kuan-Lun CHENG
  • Publication number: 20190164772
    Abstract: A method of reducing corner rounding during patterning of a substrate to form a prescribed pattern comprising a corner includes dividing the pattern into a first pattern and a second pattern, the first pattern forming a first edge of the corner and the second pattern forming a second edge of the corner. At least a portion of the second pattern overlaps the first pattern such that the first edge intersects with the second edge to form a corner of the prescribed pattern. The method further includes forming the first pattern in a first mask layer disposed on a substrate to expose the substrate and forming the second pattern in the first mask layer to expose the substrate. The substrate exposed through the first mask layer is then etched to obtain the pattern.
    Type: Application
    Filed: April 30, 2018
    Publication date: May 30, 2019
    Inventors: Chin-Yuan TSENG, Yu-Tien SHEN, Wei-Liang LIN, Chih-Ming LAI, Kuo-Cheng CHING, Shi Ning JU, Li-Te LIN, Ru-Gun LIU