Abstract: A processing path generating device including an intuitive path teaching device and a controller is provided. The intuitive path teaching device is provided for gripping and moving with respect to a workpiece to create a moving path. The intuitive path teaching device has a detecting portion for detecting a surface feature of the workpiece. The controller is connected to the intuitive path teaching device. The controller generates a processing path according to the moving path of the intuitive path teaching device and the surface feature of the workpiece.

Abstract: A cross laser calibration device used to calibrate a tool center point is provided. The calibration device includes a coordinate orifice plate, a set of cross laser sensors and a rotational and translational movement mechanism. The coordinate orifice plate has an orifice center point. The set of cross laser sensors is arranged on the coordinate orifice plate to generate cross laser lines intersecting at the orifice center point. The set of cross laser sensors is driven by the second motor to rotate around the center point of the second motor, wherein the orifice center point has an off-axis setting relative to the center point of the second motor.

Abstract: A manufacturing method of a memory device are provided. The method includes following steps. A gate stacking structure is formed over a substrate. A first insulating layer, a second insulating layer and a mask material layer are sequentially formed over the substrate to cover the gate stacking structure. An ion implantation process is performed on the mask material layer to form a doped portion in the mask material layer. The doped portion caps on a top portion of the gate stacking structure. A first patterning process is performed on the mask material layer using the doped portion as a shadow mask to remove a bottom portion of the mask material layer extending along a surface of the substrate. A second patterning process is performed to remove the doped portion of the mask material layer and an exposed bottom portion of the second insulating layer surrounding the gate stacking structure.

Abstract: A structure of a three-phase motor is provided. The structure of the three-phase motor includes a stator, a rotor, first-phase windings, second-phase windings, and third-phase windings. In one embodiment, the stator has fifteen winding groove bodies, and the rotor has seven magnetic element pairs. In another embodiment, the stator has twenty-one winding groove bodies, and the rotor has ten magnetic element pairs. The first-phase windings are disposed in first winding groove bodies, and the first winding groove bodies are disposed adjacent to each other. The second-phase windings are disposed in second winding groove bodies, and the second winding groove bodies are disposed adjacent to each other. The third-phase windings are disposed in third winding groove bodies, and the third winding groove bodies are disposed adjacent to each other.

Abstract: Apparatuses and systems for damping vibration of a vacuum vessel mounted with a pump include a pump body and a damping element coupled to the pump body, wherein the pump body and the damping element form a mass-based damper, and wherein the pump body forms a mass component of the mass-based damper; and the damping element forms a damping component of the mass-based damper. The apparatuses and systems also include a pump body configured to be secured to a column of a charged-particle inspection apparatus, a sensor coupled to the pump body, an actuator coupled to the pump body, and a circuitry communicatively coupled to the sensor and the actuator for receiving motion data indicative of a vibration of the column; determining a damping based on the motion data; and actuate the actuator to react to the vibration of the column in accordance with the damping.

Abstract: An electronic device and a method of controlling multiple pieces of equipment are provided. The electronic device is coupled to an operating device, a first controlled device and a second controlled device. The electronic device includes an operating interface and a controlled interface. The operating interface is coupled to the operating device. The operating device includes a first operating area and a second operating area. The first operating area is configured to deliver a first operating signal. The second operating area is configured to deliver a second operating signal. The controlled interface is coupled to the first controlled device and the second controlled device. The first controlled device is controlled by the first operating signal. The second controlled device is controlled by the second operating signal.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. The semiconductor device includes a first channel members being vertically stacked, a second channel members being vertically stacked, an n-type work function layer wrapping around each of the first channel members, a first p-type work function layer over the n-type work function layer and wrapping around each of the first channel members, a second p-type work function layer wrapping around each of the second channel members, a third p-type work function layer over the second p-type work function layer and wrapping around each of the second channel members, and a gate cap layer over a top surface of the first p-type work function layer and a top surface of the third p-type work function layer such that the gate cap layer electrically couples the first p-type work function layer and the third p-type work function layer.

Abstract: A semiconductor device includes a stack of semiconductor layers vertically arranged above a semiconductor base structure, a gate dielectric layer having portions each surrounding one of the semiconductor layers, and a gate electrode surrounding the gate dielectric layer. Each portion of the gate dielectric layer has a top section above the respective semiconductor layer and a bottom section below the semiconductor layer. The top section has a top thickness along a vertical direction perpendicular to a top surface of the semiconductor base structure; and the bottom section has a bottom thickness along the vertical direction. The top thickness is greater than the bottom thickness.

Abstract: A method includes providing a structure having a first channel member and a second channel member over a substrate. The first channel member is located in a first region of the structure and the second channel member is located in a second region of the structure. The method also includes forming a first oxide layer over the first channel member and a second oxide layer over the second channel member, forming a first dielectric layer over the first oxide layer and a second dielectric layer over the second oxide layer, and forming a capping layer over the second dielectric layer but not over the first dielectric layer. The method further includes performing an annealing process to increase a thickness of the second oxide layer under the capping layer.

Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.

Abstract: An n-type field effect transistor includes semiconductor channel members vertically stacked over a substrate, a gate dielectric layer wrapping around each of the semiconductor channel members, and a work function layer disposed over the gate dielectric layer. The work function layer wraps around each of the semiconductor channel members. The n-type field effect transistor also includes a WF isolation layer disposed over the WF layer and a gate metal fill layer disposed over the WF isolation layer. The WF isolation layer fills gaps between adjacent semiconductor channel members.

Abstract: A semiconductor device is provided, which includes a first semiconductor structure, a second semiconductor structure, and an active region. The first semiconductor structure includes a first dopant. The second semiconductor structure is located on the first semiconductor structure and includes a second dopant different from the first dopant. The active region includes a plurality of semiconductor pairs and is located between the first semiconductor structure and the second semiconductor structure. One of the plurality of semiconductor pairs has a barrier layer and a well layer and includes the first dopant. The barrier layer has a first thickness and a first Al content, and the well layer has a second thickness and a second Al content, the second thickness is less than the first thickness, and the second Al content is less than the first Al content.

Abstract: An ion mobility spectrometry-mass spectrometry combined analysis device includes an ionization source producing target analyte ions; an ion mobility filter receiving at least a part of the target analyte ions from the ionization source and operating in a sub-atmospheric environment to select ions within a specified mobility range from the target analyte ions to pass; and a mass filter connected to the rear stage of the ion mobility filter selecting ions in a specified mass-to-charge ratio range from the ions within the specified mobility range to pass. The ion mobility spectrometry-mass spectrometry combined device can separate the target ions based on a collision cross section under the combined action of a scanning electric field and an external gas flow, and operate at low gas pressure, which improves the efficiency of target analysis and an intra-spectrum dynamic range, and perform highly reliable and accurate quantitative analysis on specific target ions.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a gate stacking structure, a first insulating layer, a second insulating layer and a first spacer. The gate stacking structure is disposed over a substrate. The first insulating layer covers a top surface and a sidewall of the gate stacking structure. The second insulating layer covers a surface of the first insulating layer. A top corner region of the gate stacking structure is covered by the first and second insulating layers. The first spacer is located on the sidewall of the gate stacking structure, and covers a surface of the second insulating layer. A topmost end of the first spacer is lower than a topmost surface of the second insulating layer.

Abstract: A back plate for rapid and fluid-assisted assembly of micro light emitting elements thereon includes a substrate with a driving circuit, and blocking walls made to protrude from a top surface of the substrate. The top surface of the substrate defines grooves for accommodating and powering micro light emitting elements. Each of the blocking walls semi-surrounds one groove and defines a notch. The notches defined by each blocking wall all face a single direction and the blocking walls and notches impede and gather micro light emitting elements which are made to flow in a fluid suspension and render them much more likely to tumble into the groove.

Abstract: A method further includes the following steps. Firstly, a three-dimensional picture under a generated background condition is generated, wherein the three-dimensional picture includes a three-dimensional object image. Then, a two-dimensional picture of the three-dimensional picture is captured, wherein the two-dimensional picture includes a two-dimensional object image of the three-dimensional object image. Then, an object region of the two-dimensional object image is recognized. Then, an exposed ratio of an exposed area of an exposed region of the object region to an object area of the object region is obtained. Then, whether the exposed ratio is greater than a preset ratio is determined. Then the exposed region is defined as the pick-and-place region when the exposed ratio is greater than the preset ratio.

Abstract: A display device includes a display and a transflective module. The transflective module is disposed at one side of the display and includes a glass substrate and a transflective structure layer. The transflective structure layer is disposed on the glass substrate and located between the glass substrate and the display.

Abstract: A semiconductor device includes stacks of nano-structures that each extend in a first horizontal direction. The stacks each extend in a vertical direction and are separated from one another in a second horizontal direction. A first gate is disposed over a first subset of the stacks. A second gate is disposed over a second subset of the stacks. A first conductive capping layer is disposed over a substantial entirety of an upper surface of the first gate. A second conductive capping layer is disposed over a substantial entirety of an upper surface of the second gate. A dielectric structure is disposed between the first gate and the second gate in the second horizontal direction. The dielectric structure physically and electrically separates the first gate and the second gate. An upper surface of the dielectric structure is substantially free of having the first or second conductive capping layers disposed thereon.

Abstract: A semiconductor device and related method for forming a gate structure. In some embodiments, a semiconductor device includes a fin extending from a substrate. In some cases, the fin includes a plurality of semiconductor channel layers. In some examples, the semiconductor device further includes a gate dielectric surrounding each of the plurality of semiconductor channel layers. In some embodiments, a first thickness of the gate dielectric disposed on a top surface of a topmost semiconductor channel layer of the plurality of semiconductor channel layers is greater than a second thickness of the gate dielectric disposed on a surface of another semiconductor channel layer disposed beneath the topmost semiconductor channel layer.

Abstract: A visual recognition based method for projecting patterned light includes: projecting a calibration image onto a projection screen by a projection module; capturing the calibration image by an image-capturing module to obtain a calibration information between the projection module and the image-capturing module; capturing an object by the image-capturing module to obtain a to-be-recognized image of the object; detecting the object in the to-be-recognized image and acquiring a plurality of feature points associated with a plurality of feature areas of the object in the to-be-recognized image; retrieving a plurality of target feature points corresponding to a target object from the feature points; obtaining a projection coordinate of the target feature points\according to the calibration information and providing the projection coordinate to the projection module; and projecting a projection pattern with shape corresponding to the target object onto the object by the projection module according to the projectio