Abstract: A semiconductor wafer includes a substrate, a first separating structure and a semiconductor stacked layer structure. The substrate has a first surface. The first separating structure is formed on the first surface to divide the first surface into a plurality of independent regions. The minimum area of each of the regions is more than or equal to one square inch. The semiconductor stacked layer structure is disposed on the first surface and the first separating structure. The semiconductor wafer can prevent bowing of the semiconductor wafer during an epitaxial growth process so as to enhance quality of the semiconductor wafer.

Abstract: An LED chip includes a substrate, a semiconductor device layer, a wall structure, and a number of electrodes. The semiconductor device layer is disposed on the substrate and includes a first-type doped semiconductor layer disposed on the substrate, an active layer disposed on a portion of the first-type doped semiconductor layer, and a second-type doped semiconductor layer disposed on the active layer and having a first top surface. The wall structure is disposed on the first-type doped semiconductor layer that is not covered by the active layer and surrounds the active layer. Besides, the wall structure has a second top surface higher than the first top surface of the second-type doped semiconductor layer. Additionally, the electrodes are disposed on and electrically connected with the first-type doped semiconductor layer and the second-type doped semiconductor layer.

Abstract: A LED chip including a substrate, a semiconductor device layer, a current blocking layer, a current spread layer, a first electrode and a second electrode is provided. The semiconductor device layer is disposed on the substrate. The current blocking layer is disposed on a part of the semiconductor device layer and includes a current blocking segment and a current distribution adjusting segment. The current spread layer is disposed on a part of the semiconductor device layer and covers the current blocking layer. The first electrode is disposed on the current spread layer, wherein a part of the current blocking segment is overlapped with the first electrode. Contours of the current blocking segment and the first electrode are similar figures. Contour of the first electrode and is within contour of the current blocking segment. The current distribution adjusting segment is not overlapped with the first electrode.

Abstract: A method for fabricating a light emitting diode chip is provided. In the method, a half-tone mask process, a gray-tone mask process or a multi-tone mask process is applied and combined with a lift-off process to further reduce process steps of the light emitting diode chip. In the present invention, some components may also be simultaneously formed by an identical process to reduce the process steps of the light emitting diode chip. Consequently, the fabricating method of the light emitting diode provided in the present invention reduces the cost and time for the fabrication of the light emitting diode.

Abstract: A method for fabricating a light emitting diode chip is provided. In the method, a half-tone mask process, a gray-tone mask process or a multi-tone mask process is applied and combined with a lift-off process to further reduce process steps of the light emitting diode chip. In the present invention, some components may also be simultaneously formed by an identical process to reduce the process steps of the light emitting diode chip. Consequently, the fabricating method of the light emitting diode provided in the present invention reduces the cost and time for the fabrication of the light emitting diode.

Abstract: A method for fabricating a light emitting diode chip is provided. In the method, a half-tone mask process, a gray-tone mask process or a multi-tone mask process is applied and combined with a lift-off process to further reduce process steps of the light emitting diode chip. In the present invention, some components may also be simultaneously formed by an identical process to reduce the process steps of the light emitting diode chip. Consequently, the fabricating method of the light emitting diode provided in the present invention reduces the cost and time for the fabrication of the light emitting diode.

Abstract: A method for fabricating a light emitting diode chip is provided. In the method, a half-tone mask process, a gray-tone mask process or a multi-tone mask process is applied and combined with a lift-off process to further reduce process steps of the light emitting diode chip. In the present invention, some components may also be simultaneously formed by an identical process to reduce the process steps of the light emitting diode chip. Consequently, the fabricating method of the light emitting diode provided in the present invention reduces the cost and time for the fabrication of the light emitting diode.

Abstract: A method for fabricating a light emitting diode chip is provided. In the method, a half-tone mask process, a gray-tone mask process or a multi-tone mask process is applied and combined with a lift-off process to further reduce process steps of the light emitting diode chip. In the present invention, some components may also be simultaneously formed by an identical process to reduce the process steps of the light emitting diode chip. Consequently, the fabricating method of the light emitting diode provided in the present invention reduces the cost and time for the fabrication of the light emitting diode.

Abstract: A method for fabricating a light emitting diode chip is provided. In the method, a half-tone mask process, a gray-tone mask process or a multi-tone mask process is applied and combined with a lift-off process to further reduce process steps of the light emitting diode chip. In the present invention, some components may also be simultaneously formed by an identical process to reduce the process steps of the light emitting diode chip. Consequently, the fabricating method of the light emitting diode provided in the present invention reduces the cost and time for the fabrication of the light emitting diode.

Abstract: A method for fabricating a light emitting diode chip is provided. In the method, a half-tone mask process, a gray-tone mask process or a multi-tone mask process is applied and combined with a lift-off process to further reduce process steps of the light emitting diode chip. In the present invention, some components may also be simultaneously formed by an identical process to reduce the process steps of the light emitting diode chip. Consequently, the fabricating method of the light emitting diode provided in the present invention reduces the cost and time for the fabrication of the light emitting diode.

Abstract: In a fabricating method of an LED, a first-type doped semiconductor material layer, a light emitting material layer, and a second-type doped semiconductor material layer are sequentially formed on a substrate. The first-type and second-type doped semiconductor material layers and the light emitting material layer are patterned to form a first-type doped semiconductor layer, an active layer, and a second-type doped semiconductor layer. The active layer is disposed on a portion of the first-type doped semiconductor layer. The second-type doped semiconductor layer is disposed on the active layer and has a first top surface. A wall structure is formed on the first-type doped semiconductor layer that is not covered by the active layer, and the wall structure surrounds the active layer and has a second top surface higher than the first top surface of the second-type doped semiconductor layer. Electrodes are formed on the first-type and second-type doped semiconductor layers.

Abstract: The invention discloses a switching element of a pixel electrode for a display device and methods for fabricating the same. A gate is formed on a substrate. A first copper silicide layer is formed on the gate. An insulating layer is formed on the first copper silicide layer. A semiconductor layer is formed on the insulating layer. A source and a drain are formed on the semiconductor layer. Moreover, a second copper silicide layer is sandwiched between the semiconductor layer and the source/drain.

Abstract: An active matrix array structure, disposed on a substrate, includes a first patterned conductive layer, a patterned gate insulating layer, a patterned semiconductor layer, a second patterned conductive layer, a patterned overcoat layer and a transparent conductive layer. The patterned gate insulating layer has first openings that expose a part of the first patterned conductive layer. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The second patterned conductive layer is disposed on the patterned semiconductor layer. The patterned overcoat layer has second openings that expose a part of the first patterned conductive layer and a part of the second patterned conductive layer. The transparent conductive layer is completely disposed on the substrate. The transparent conductive layer disposed in the first openings and the second openings is broken off at a position that is in between the substrate and the patterned overcoat layer.

Abstract: An active device array substrate and its fabricating method are provided. According to the subject invention, the elements of an array substrate such as the thin film transistors, gate lines, gate pads, data lines, data pads and storage electrodes, are provided by forming a patterned first metal layer, an insulating layer, a patterned semiconductor layer and a patterned metal multilayer. Furthermore, the subject invention uses the means of selectively etching certain layers. Using the aforesaid means, the array substrate of the subject invention has some layers with under-cut structures, and thus, the number of the time-consuming and complicated mask etching process involved in the production of an array substrate can be reduced. The subject invention provides a relatively simple and time-saving method for producing an array substrate.

Abstract: A method for fabricating a pixel structure includes following steps. First, a substrate is provided. Next, a first conductive layer is formed on the substrate. Next, a first shadow mask is disposed over the first conductive layer. Next, a laser is applied through the first shadow mask to irradiate the first conductive layer to form a gate. Next, a gate dielectric layer is formed on the substrate to cover the gate. After that, a channel layer, a source and a drain are simultaneously formed on the gate dielectric layer over the gate, wherein the gate, the channel layer, the source and the drain together form a thin film transistor. A patterned passivation layer is formed on the thin film transistor and the patterned passivation layer exposes a part of the drain. Furthermore, a pixel electrode electrically connecting to the drain is formed.

Abstract: A method for manufacturing a pixel structure is provided. A gate and a gate insulating layer are sequentially formed on a substrate. A semiconductor layer and a second metal layer are sequentially formed on the gate insulating layer. The semiconductor layer and the second metal layer are patterned to form a channel layer, a source and a drain by using a patterned photoresist layer formed thereon, wherein the source and drain are disposed on a portion of the channel layer. The gate, channel, source and drain form a thin film transistor. A passivation layer is formed on the patterned photoresist layer, the gate insulating layer and the thin film transistor. Then, the patterned photoresist layer is removed, such that the passivation layer thereon is removed simultaneously to form a patterned passivation layer and the drain is exposed. A pixel electrode is formed on the patterned passivation layer and the drain.

Abstract: A method for forming a semiconductor layer includes following steps. First, an epitaxial substrate having at least a first growth region and at least a second growth region is provided. An area ratio of C plane to R plane in the first growth region is greater than 52/48. An epitaxial process is then performed on the epitaxial substrate to form a semiconductor layer. During the epitaxial process, a semiconductor material is selectively grown on the first growth region, and then the semiconductor material is laterally overgrown on the second growth region and covers the same.

Abstract: The invention discloses a switching device for a pixel electrode of display device. The switching device comprises a gate formed on a substrate; a gate-insulating layer formed on the gate; a first buffer layer formed between the substrate and the gate and/or between the gate and the gate-insulating layer, wherein the first buffer layer comprises TaSix, TaSixNy, TiSix, TiSixNy, WSix, WSixNy, or WCxNy; a semiconductor layer formed on a portion of the gate-insulating layer; and a source and a drain formed on a portion of the semiconductor layer.

Abstract: An active matrix array structure, disposed on a substrate, includes a first patterned conductive layer, a patterned gate insulating layer, a patterned semiconductor layer, a second patterned conductive layer, a patterned overcoat layer and a transparent conductive layer. The patterned gate insulating layer has first openings that expose a part of the first patterned conductive layer. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The second patterned conductive layer is disposed on the patterned semiconductor layer. The patterned overcoat layer has second openings that expose a part of the first patterned conductive layer and a part of the second patterned conductive layer. The transparent conductive layer is completely disposed on the substrate. The transparent conductive layer disposed in the first openings and the second openings is broken off at a position that is in between the substrate and the patterned overcoat layer.

Abstract: An active device array substrate and its fabricating method are provided. According to the subject invention, the elements of an array substrate such as the thin film transistors, gate lines, gate pads, data lines, data pads and storage electrodes, are provided by forming a patterned first metal layer, an insulating layer, a patterned semiconductor layer and a patterned metal multilayer. Furthermore, the subject invention uses the means of selectively etching certain layers. Using the aforesaid means, the array substrate of the subject invention has some layers with under-cut structures, and thus, the number of the time-consuming and complicated mask etching process involved in the production of an array substrate can be reduced. The subject invention provides a relatively simple and time-saving method for producing an array substrate.