Patents by Inventor Kurtis LESCHKIES
Kurtis LESCHKIES has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20220013375Abstract: Embodiments of the disclosure relate to an apparatus and method for annealing one or more semiconductor substrates. In one embodiment, a processing chamber is disclosed. The processing chamber includes a chamber body enclosing an internal volume, a substrate support disposed in the internal volume and configured to support a substrate during processing, a gas panel configured to provide a processing fluid into the internal volume, and a temperature-controlled fluid circuit configured to maintain the processing fluid at a temperature above a condensation point of the processing fluid. The temperature-controlled fluid circuit includes a gas conduit fluidly coupled to a port on the chamber body at a first end and to the gas panel at a second end.Type: ApplicationFiled: May 25, 2021Publication date: January 13, 2022Inventors: Jean DELMAS, Steven VERHAVERBEKE, Kurtis LESCHKIES
-
Patent number: 11177128Abstract: Methods for forming a semiconductor structure including a silicon (Si) containing layer or a silicon germanium (SiGe) layer are provided. The methods include depositing a protective barrier (e.g., liner) layer over the semiconductor structure, forming a flowable dielectric layer over the liner layer, and exposing the flowable dielectric layer to high pressure steam. A cluster system includes a first deposition chamber configured to form a semiconductor structure, a second deposition chamber configured to perform a liner deposition process to form a liner layer, a third deposition chamber configured to form a flowable dielectric layer over the liner layer, an annealing chamber configured to expose the flowable oxide layer to high pressure steam.Type: GrantFiled: September 11, 2018Date of Patent: November 16, 2021Assignee: Applied Materials, Inc.Inventors: Pramit Manna, Abhijit Basu Mallick, Kurtis Leschkies, Steven Verhaverbeke, Shishi Jiang
-
Publication number: 20210346983Abstract: A method of fabricating a frame to enclose one or more semiconductor dies includes forming one or more features including one or more cavities and one or more through-vias in a substrate by a first laser ablation process, filling the one or more through-vias with a dielectric material, and forming a via-in-via in the dielectric material filled in each of the one or more through-vias by a second laser ablation process. The one or more cavities is configured to enclose one or more semiconductor dies therein. In the first laser ablation process, frequency, pulse width, and pulse energy of a first pulsed laser beam to irradiate the substrate are tuned based on a depth of the one or more features. In the second laser ablation process, frequency, pulse width, and pulse energy of a second pulsed laser beam to irradiate the dielectric material are tuned based on a depth of the via-in-via.Type: ApplicationFiled: May 11, 2020Publication date: November 11, 2021Inventors: Kurtis LESCHKIES, Wei-Sheng LEI, Jeffrey L. FRANKLIN, Jean DELMAS, Han-Wen CHEN, Giback PARK, Steven VERHAVERBEKE
-
Publication number: 20210288027Abstract: The present disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, embodiments described herein relate to semiconductor device spacers and methods of forming the same. The semiconductor device spacers described herein may be utilized to form stacked semiconductor package assemblies, stacked PCB assemblies, and the like.Type: ApplicationFiled: March 10, 2020Publication date: September 16, 2021Inventors: Kurtis LESCHKIES, Han-Wen CHEN, Steven VERHAVERBEKE, Giback PARK, Kyuil CHO, Jeffrey L. FRANKLIN, Wei-Sheng LEI
-
Publication number: 20210257289Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.Type: ApplicationFiled: April 12, 2021Publication date: August 19, 2021Inventors: Han-Wen CHEN, Steven VERHAVERBEKE, Giback PARK, Kyuil CHO, Kurtis LESCHKIES, Roman GOUK, Chintan BUCH, Vincent DICAPRIO, Bernhard STONAS, Jean DELMAS
-
Publication number: 20210249345Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.Type: ApplicationFiled: April 12, 2021Publication date: August 12, 2021Inventors: Han-Wen CHEN, Steven VERHAVERBEKE, Giback PARK, Kyuil CHO, Kurtis LESCHKIES, Roman GOUK, Chintan BUCH, Vincent DICAPRIO, Bernhard STONAS, Jean DELMAS
-
Publication number: 20210159160Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.Type: ApplicationFiled: May 28, 2020Publication date: May 27, 2021Inventors: Han-Wen CHEN, Steven VERHAVERBEKE, Giback PARK, Kyuil CHO, Kurtis LESCHKIES, Roman GOUK, Chintan BUCH, Vincent DICAPRIO, Bernhard STONAS, Jean DELMAS
-
Publication number: 20210159158Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.Type: ApplicationFiled: November 27, 2019Publication date: May 27, 2021Inventors: Han-Wen CHEN, Steven VERHAVERBEKE, Giback PARK, Kyuil CHO, Kurtis LESCHKIES, Roman GOUK, Chintan BUCH, Vincent DICAPRIO
-
Patent number: 11018032Abstract: Embodiments of the disclosure relate to an apparatus and method for annealing one or more semiconductor substrates. In one embodiment, a processing chamber is disclosed. The processing chamber includes a chamber body enclosing an internal volume, a substrate support disposed in the internal volume and configured to support a substrate during processing, a gas panel configured to provide a processing fluid into the internal volume, and a temperature-controlled fluid circuit configured to maintain the processing fluid at a temperature above a condensation point of the processing fluid. The temperature-controlled fluid circuit includes a gas conduit fluidly coupled to a port on the chamber body at a first end and to the gas panel at a second end.Type: GrantFiled: April 8, 2019Date of Patent: May 25, 2021Assignee: APPLIED MATERIALS, INC.Inventors: Jean Delmas, Steven Verhaverbeke, Kurtis Leschkies
-
Patent number: 10937726Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.Type: GrantFiled: January 17, 2020Date of Patent: March 2, 2021Assignee: Applied Materials, Inc.Inventors: Han-Wen Chen, Steven Verhaverbeke, Giback Park, Kyuil Cho, Kurtis Leschkies, Roman Gouk, Chintan Buch, Vincent DiCaprio
-
Publication number: 20200388486Abstract: Methods for forming a semiconductor structure including a silicon (Si) containing layer or a silicon germanium (SiGe) layer are provided. The methods include depositing a protective barrier (e.g., liner) layer over the semiconductor structure, forming a flowable dielectric layer over the liner layer, and exposing the flowable dielectric layer to high pressure steam. A cluster system includes a first deposition chamber configured to form a semiconductor structure, a second deposition chamber configured to perform a liner deposition process to form a liner layer, a third deposition chamber configured to form a flowable dielectric layer over the liner layer, an annealing chamber configured to expose the flowable oxide layer to high pressure steam.Type: ApplicationFiled: September 11, 2018Publication date: December 10, 2020Inventors: Pramit MANNA, Abhijit Basu MALLICK, Kurtis LESCHKIES, Steven VERHAVERBEKE, Shishi JIANG
-
Patent number: 10818490Abstract: Implementations described herein generally relate to methods for forming a low-k dielectric material on a semiconductor substrate. More specifically, implementations described herein relate to methods of forming a silicon oxide film at high pressure and low temperatures. In one implementation, a method of forming a silicon oxide film is provided. The method comprises loading a substrate having a silicon-containing film formed thereon into a processing region of a high-pressure vessel. The method further comprises forming a silicon oxide film on the silicon-containing film. Forming the silicon oxide film on the silicon-containing film comprises exposing the silicon-containing film to a processing gas comprising steam at a pressure greater than about 1 bar and maintaining the high-pressure vessel at a temperature between about 100 degrees Celsius and about 500 degrees Celsius.Type: GrantFiled: November 27, 2018Date of Patent: October 27, 2020Assignee: Applied Materials, Inc.Inventors: Shishi Jiang, Kurtis Leschkies, Pramit Manna, Abhijit Basu Mallick, Steven Verhaverbeke
-
Patent number: 10790183Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure is oxidized by a high pressure oxidation process to form a buried oxide layer adjacent the substrate.Type: GrantFiled: May 9, 2019Date of Patent: September 29, 2020Assignee: Applied Materials, Inc.Inventors: Shiyu Sun, Keith Tatseun Wong, Kurtis Leschkies, Namsung Kim, Srinivas Nemani
-
Publication number: 20200243345Abstract: Disclosed herein is an apparatus and method for annealing semiconductor substrates. In one example a temperature-controlled fluid circuit includes a condenser configured to fluidly connect to an internal volume of a processing chamber. The processing chamber has a body, the internal volume is within the body. The condenser is configured to condense a processing fluid into liquid phase. A source conduit includes a first terminal end that couples to a first port on the body of the processing chamber. The source conduit includes a second terminal end. The first terminal end couples to a gas panel. The gas panel is configured to provide a processing fluid into the internal volume of the processing chamber. A gas conduit includes a first end. The first end couples to the condenser and a second end. The second end is configured to couple to a second port on the body of the processing chamber.Type: ApplicationFiled: April 15, 2020Publication date: July 30, 2020Inventors: Jean DELMAS, Steven VERHAVERBEKE, Kurtis LESCHKIES
-
Publication number: 20200234973Abstract: Disclosed herein is an apparatus and method for annealing semiconductor substrates. In one example the method of annealing substrates in a processing chamber includes loading a plurality of substrates into an internal volume of the processing chamber. The method includes flowing a processing fluid through a gas conduit into the internal volume. The method further includes measuring a temperature of the gas conduit at one or more position utilizing one or more temperature sensors. The processing fluid in the gas conduit and the internal volume are maintained at a temperature above a condensation point of the processing fluid.Type: ApplicationFiled: April 7, 2020Publication date: July 23, 2020Inventors: Jean DELMAS, Steven VERHAVERBEKE, Kurtis LESCHKIES
-
Publication number: 20200161178Abstract: Embodiments described herein relate to methods of seam-free gapfilling and seam healing that can be carried out using a chamber operable to maintain a supra-atmospheric pressure (e.g., a pressure greater than atmospheric pressure). One embodiment includes positioning a substrate having one or more features formed in a surface of the substrate in a process chamber and exposing the one or more features of the substrate to at least one precursor at a pressure of about 1 bar or greater. Another embodiment includes positioning a substrate having one or more features formed in a surface of the substrate in a process chamber. Each of the one or more features has seams of a material. The seams of the material are exposed to at least one precursor at a pressure of about 1 bar or greater.Type: ApplicationFiled: November 6, 2019Publication date: May 21, 2020Inventors: Shishi JIANG, Kurtis LESCHKIES, Pramit MANNA, Abhijit MALLICK
-
Patent number: 10636705Abstract: The method of treating a film stack includes depositing a barrier film containing a metal into a via formed within a dielectric layer disposed on a substrate and depositing a metal contact on the barrier film within the via, where a void is located within the barrier film or between the barrier film and the metal contact. The method also includes exposing the metal contact and the barrier film to an oxidizing agent at a temperature of less than 400° C. and at a pressure of about 20 bar to about 100 bar within a process chamber to produce a metal oxide within the void.Type: GrantFiled: November 29, 2018Date of Patent: April 28, 2020Assignee: APPLIED MATERIALS, INC.Inventors: Yifei Wang, Kurtis Leschkies, Fei Wang, Xin Liu, Wei Tang, Yixiong Yang, Wenyi Liu, Ludovic Godet
-
Patent number: 10636677Abstract: Embodiments of the disclosure relate to an apparatus and method for annealing semiconductor substrates. In one embodiment, a batch processing chamber is disclosed. The batch processing chamber includes a chamber body enclosing a processing region, a gas panel configured to provide a processing fluid into the processing region, a condenser fluidly connected to the processing region and a temperature-controlled fluid circuit configured to maintain the processing fluid at a temperature above a condensation point of the processing fluid. The processing region is configured to retain a plurality of substrates during processing. The condenser is configured to condense the processing fluid into a liquid phase.Type: GrantFiled: July 26, 2018Date of Patent: April 28, 2020Assignee: Applied Materials, Inc.Inventors: Jean Delmas, Steven Verhaverbeke, Kurtis Leschkies
-
Patent number: 10636669Abstract: Aspects of the disclosure include methods of processing a substrate. The method includes depositing a conformal layer on a substrate which contains seams. The substrate is treated using a high pressure anneal in the presence of an oxidizer.Type: GrantFiled: January 14, 2019Date of Patent: April 28, 2020Assignee: APPLIED MATERIALS, INC.Inventors: Yihong Chen, Rui Cheng, Pramit Manna, Abhijit Basu Mallick, Shishi Jiang, Yong Wu, Kurtis Leschkies, Srinivas Gandikota
-
Patent number: 10559496Abstract: A method of device processing. The method may include providing a cavity in a layer, directing energetic flux to a bottom surface of the cavity, performing an exposure of the cavity to a moisture-containing ambient, and introducing a fill material in the cavity using an atomic layer deposition (ALD) process, wherein the fill material is selectively deposited on the bottom surface of the cavity with respect to a sidewall of the cavity.Type: GrantFiled: February 23, 2018Date of Patent: February 11, 2020Assignee: APPLIED MATERIALS, INC.Inventors: Kurtis Leschkies, Steven Verhaverbeke