Abstract: An optical device may include a substrate including a conductive core, a first layer stack on a first surface of the conductive core, a conductor-filled trench extending through the first layer stack to the conductive core such that the conductor-filled trench is on the first surface of the conductive core, and a second layer stack on a second surface of the conductive core. The optical device may include a vertical-cavity surface-emitting laser (VCSEL) chip above the conductor-filled trench. The VCSEL chip may include an array of VCSELs. A size of the conductor-filled trench may match a size of the VCSEL chip, match a size of an emission region of the array of VCSELs, or be greater than the size of the emission region of the array of VCSELs and less than the size of the VCSEL chip.

Abstract: In some implementations, an emitter assembly includes a vertical cavity surface emitting laser (VCSEL) device. The VCSEL device may include a substrate. The VCSEL device may include a plurality of VCSELs on the substrate. The VCSEL device may include at least one anode layer on the substrate and electrically connected to the plurality of VCSELs. The VCSEL device may include a cathode electrode over at least a portion of multiple VCSELs, of the plurality of VCSELs, and electrically connected to the multiple VCSELs. The cathode electrode may include multiple cathode electrode fingers. The emitter assembly may include a bridge element that electrically connects a first finger of the multiple cathode electrode fingers and a second finger of the multiple cathode electrode fingers.

Abstract: In some implementations, a vertical cavity surface emitting laser (VCSEL) device includes a substrate and a plurality of VCSELs on the substrate. The VCSEL device may include an anode layer on the substrate and electrically connected to the plurality of VCSELs. The VCSEL device may include a cathode electrode over at least a portion of one or more VCSELs, of the plurality of VCSELs, and electrically connected to the one or more VCSELs. The VCSEL device may include a ground layer electrically isolated from the at least one anode layer and the cathode electrode by one or more isolation layers, wherein the ground layer is on the anode layer and the cathode electrode, between the anode layer and the cathode electrode, or underneath the anode layer.

Abstract: This invention provides an alloy with an interference thin film and the method for making the same. In one embodiment, said alloy consists essentially of 55.0-78.0 wt % Au, 8.0-24.0 wt % Ag, 8.0-24.0 wt % Cu and 0.0-3.0 wt % deoxidizer, and said interference thin film is grown on a surface of said alloy and has a thickness of less than 200 nm; wherein said interference thin film exhibits a patination color.

Abstract: This invention provides an amorphous alloy. In one embodiment, the amorphous alloy consists essentially of: i) 52.55-80.12 at. % of Au; ii) 11.74-15.55 at. % of Ge; iii) 8.13-10.77 at. % of Si; iv) 5-21.13 at. % being at least one element selected from the group consisting of Ag, Bi, Pd and Pt.

Abstract: A substrate may include a thermally conductive metal core having a top side and a bottom side, a first dielectric coating on the top side of the metal core, a second dielectric coating on the bottom side of the metal core, a first metal circuit layer formed above the first dielectric coating, and a second metal circuit layer formed under the second dielectric coating. In some implementations, the first dielectric coating and the second dielectric coating have thicknesses below sixty micrometers and respective thermal resistances under fifteen degrees Celsius per watt. In some implementations, one or more electrical currents flowing vertically across a dielectric coating have a low parasitic inductance based on the thickness of the dielectric coating, and the metal core may dissipate heat flowing across the dielectric coating and into the metal core.

Abstract: In particles removal with extremely high filtration efficiency and the ability to block submicron airborne particles by a sieving mechanism is provided. This novel nanoporous filter advantageously combines extremely high transmittance for visible light and ultraviolet light, reusability after cleaning or disinfection by ultraviolet irradiation or simple washing, a customizable sieving pore size ranging from a few nanometers to 500 nanometers, and the ability to carry bactericidal, virucidal or other reagents or particles on the nano or micro scale.

Abstract: An optical assembly includes an integrated circuit (IC) driver chip; an optical subassembly disposed on the IC driver chip that includes: a vertical cavity surface emitting laser (VCSEL) device, an optical element disposed above a top surface of the VCSEL device, and two or more attachment structures disposed between the VCSEL device and the optical element; and two or more additional attachment structures disposed between the IC driver chip and the optical subassembly. The VCSEL device includes: a cathode contact disposed on the top surface of the VCSEL device, and an anode contact disposed on the top surface of the VCSEL device. The optical element includes two or more conductive traces on a bottom surface of the optical element. The two or more attachment structures are disposed between the two or more conductive traces of the optical element, and the cathode contact and the anode contact of the VCSEL device.

Abstract: In some implementations, a vertical cavity surface emitting laser (VCSEL) package may include a substrate. The VCSEL package may include a VCSEL disposed on a surface of the substrate. The VCSEL package may include a VCSEL driver disposed on the surface of the substrate. The VCSEL package may include an embedded capacitor electrically connected to the VCSEL and the VCSEL driver. The embedded capacitor may be formed from a subset of layers of the substrate. The capacitor may be associated with a first capacitance that is different from a second capacitance of at least one other capacitor associated with the substrate.

Abstract: In some implementations, an optical assembly includes a substrate that includes a thermally conductive core, an IC driver chip that is disposed on a first surface of the substrate, and a VCSEL device that includes an electrically insulated surface that is disposed on the thermally conductive core of the substrate within a cavity formed in the second surface of the substrate. The VCSEL device includes a cathode contact disposed on a surface of the VCSEL device and an anode contact disposed on the surface of the VCSEL device. The VCSEL device includes a plurality of emitters and a microlens component that is disposed over the plurality of emitters on the surface of the VCSEL device.

Abstract: An optical assembly includes a substrate; an optical subassembly that is disposed on a region of a surface of the substrate; a housing that is disposed on another region of the surface of the substrate; a first optical element that is disposed on a first support component of the housing; and a second optical element that is disposed on a second support component of the housing. The optical subassembly includes an integrated circuit (IC) driver chip; a redistribution layer (RDL) structure that is disposed on a surface of the IC driver chip, wherein the RDL structure includes a cavity; and a vertical cavity surface emitting laser (VCSEL) device disposed on a region of the surface of the RDL structure that is within the cavity of the RDL structure.

Abstract: A circuit (e.g., for use in a time-of-flight camera projector module) may include a top metal layer having an anode and a cathode, one or more capacitors connected to the anode, a vertical-cavity surface-emitting laser connected to the anode and the cathode, and a driver connected to the cathode. The circuit may further include a bottom metal layer connected to ground and arranged below the top metal layer, and a dielectric layer separating the top metal layer and the bottom metal layer. In some implementations, the dielectric layer has a thickness under sixty micrometers and a thermal resistance under fifteen degrees Celsius per watt. Accordingly, a current loop flowing vertically across the dielectric layer has a low self-inductance based on the thickness of the dielectric layer and the bottom metal layer is arranged to dissipate heat generated by the current loop flowing vertically across the dielectric layer.

Abstract: A substrate may include a thermally conductive metal core having a top side and a bottom side, a first dielectric coating on the top side of the metal core, a second dielectric coating on the bottom side of the metal core, a first metal circuit layer formed above the first dielectric coating, and a second metal circuit layer formed under the second dielectric coating. In some implementations, the first dielectric coating and the second dielectric coating have thicknesses below sixty micrometers and respective thermal resistances under fifteen degrees Celsius per watt. In some implementations, one or more electrical currents flowing vertically across a dielectric coating have a low parasitic inductance based on the thickness of the dielectric coating, and the metal core may dissipate heat flowing across the dielectric coating and into the metal core.

Abstract: In some implementations, a driver circuit may include a source to provide an electrical input, and an array of optical emitters arranged in one or more rows and one or more columns. The array may include an optical emitter associated with a row and a column. The driver circuit may include a first switch having an open state and a closed state, and an inductive element connected to the row. The first switch in the closed state may cause current to charge the inductive element. The driver circuit may include a second switch having an open state and a closed state. The second switch in the closed state may select the column. The first switch transitioning from the closed state to the open state may cause the inductive element to discharge current through the row, and through the column when the second switch is in the closed state.

Abstract: There is provided an artificial anatomical model for simulating a cricothyroidotomy procedure. The model comprises an upper body structure including a neck member with a tracheal access window spanned by a membrane. Disposed within the neck member is an anatomically accurate larynx-trachea structure under the membrane. This structure comprises a first member of a rigid first material shaped and dimensioned to define a cricothyroid space overlying an incisable artificial cricothyroid membrane material of a second member which is received therein. The second member member seals off an expansible chamber in fluid communication therewith.

Abstract: An optical chip may include a vertical-cavity surface-emitting laser (VCSEL) structure. The optical chip may include a capacitor over at least a portion of an active layer of the VCSEL structure that is outside of an active region of the VCSEL structure. The capacitor may include a first metal layer over the portion of the active layer, a dielectric layer on the first metal layer, and a second metal layer on the dielectric layer. The optical chip may include an isolation region between a substrate of the VCSEL and a portion of the capacitor outside of the VCSEL.

Abstract: An optical device may include a substrate including a conductive core, a first layer stack on a first surface of the conductive core, a conductor-filled trench extending through the first layer stack to the conductive core such that the conductor-filled trench is on the first surface of the conductive core, and a second layer stack on a second surface of the conductive core. The optical device may include a vertical-cavity surface-emitting laser (VCSEL) chip above the conductor-filled trench. The VCSEL chip may include an array of VCSELs. A size of the conductor-filled trench may match a size of the VCSEL chip, match a size of an emission region of the array of VCSELs, or be greater than the size of the emission region of the array of VCSELs and less than the size of the VCSEL chip.

Abstract: A wafer testing system may comprise a chuck, a wafer carrier, a cathode plate, and a probe card. The chuck may be configured to hold the wafer carrier. The wafer carrier may be configured to hold a wafer on a surface of the wafer carrier, wherein the surface of the wafer carrier comprises one or more contact features protruding from the surface of the wafer carrier. The cathode plate may be configured to provide an electrical connection between the wafer carrier and the probe card, wherein a portion of a surface of the cathode plate is configured to be disposed on the one or more contact features of the wafer carrier. The probe card may be configured to test, using one or more probes associated with the probe card, the wafer when the wafer is on the surface of the wafer carrier.

Abstract: A wafer testing system may comprise a chuck, a wafer carrier, a cathode plate, and a probe card. The chuck may be configured to hold the wafer carrier. The wafer carrier may be configured to hold a wafer on a surface of the wafer carrier, wherein the surface of the wafer carrier comprises one or more contact features protruding from the surface of the wafer carrier. The cathode plate may be configured to provide an electrical connection between the wafer carrier and the probe card, wherein a portion of a surface of the cathode plate is configured to be disposed on the one or more contact features of the wafer carrier. The probe card may be configured to test, using one or more probes associated with the probe card, the wafer when the wafer is on the surface of the wafer carrier.

Abstract: The present disclosure relates to a method for image patch selection for training a neural network for image quality assessment. The method includes receiving an input image and extracting one or more image patches from the input image. The moment of the extracted image patches is measured. There is a decision to accept or decline the extracted image patches according to the measured moment. Additional image patches are extracted until a minimum number, Nmin, of extracted image patches are accepted. Alternatively, selection criteria are adjusted until the minimum number of extracted image patches are accepted. The selected image patches are input into a neural network with a corresponding image quality value of the input image, and the neural network is trained with the image patches and image quality value. Also provided is a method for image quality assessment using a neural network trained as set forth above.