Abstract: A memory-containing die includes a three-dimensional memory array, a memory dielectric material layer located on a first side of the three-dimensional memory array, and memory-side bonding pads. A logic die includes a peripheral circuitry configured to control operation of the three-dimensional memory array, logic dielectric material layers located on a first side of the peripheral circuitry, and logic-side bonding pads included in the logic dielectric material layers. The logic-side bonding pads includes a pad-level mesh structure electrically connected to a source power supply circuit within the peripheral circuitry and containing an array of discrete openings therethrough, and discrete logic-side bonding pads. The logic-side bonding pads are bonded to a respective one, or a respective subset, of the memory-side bonding pads. The pad-level mesh structure can be used as a component of a source power distribution network.

Abstract: Disclosed is a three-dimensional semiconductor device including a stack structure on a substrate and including electrodes that are vertically stacked on top of each other on a first region of a substrate, a vertical structure penetrating the stack structure and including a first semiconductor pattern, a data storage layer between the first semiconductor pattern and at least one of the electrodes, a transistor on a second region of the substrate, and a first contact coupled to the transistor. The first contact includes a first portion and a second portion on the first portion. Each of the first portion and the second portions has a diameter that increases with an increasing vertical distance from the substrate. A diameter of an upper part of the first portion is greater than a diameter of a lower part of the second portion.

Abstract: A vertical memory device includes a substrate having a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, and forming a stepped structure in the connection region, a first metal line dividing the plurality of gate electrode layers and connected to the cell array region and the connection region of the substrate, and a second metal line dividing a portion of the plurality of gate electrode layers and connected to the connection region of the substrate. A depth of a lower end portion of the second metal line may be greater than a depth of a lower end portion of the first metal line in the cell array region, based on an upper surface of the substrate.

Abstract: A semiconductor device includes: an integrated circuit (IC) including an internal circuit; and a mismatch detection and correction circuit connected to the internal circuit of the IC, the mismatch detection and correction circuit configured to detect a process mismatch and correct an error in the internal circuit caused by the process mismatch using a current difference between a first current and a second current based on a charged voltage of a capacitor.

Abstract: A reference voltage generating circuit includes: an operational amplifier including a first input terminal connected to a first node and a second input terminal connected to a second node; a first transistor connected between a ground terminal and the first node, wherein a first current flows in the first transistor; a second transistor connected to the ground terminal; and a first variable resistor connected between the second transistor and the second node, wherein the first variable resistor has a first resistance value for adjusting the first current, based on a change in a current characteristic of the first transistor caused by a variation in a process of forming the first transistor. The reference voltage generating circuit provides a reference voltage, based on a voltage of the first node and a voltage across the first variable resistor.

Abstract: A vertical memory device includes a substrate having a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, and forming a stepped structure in the connection region, a first metal line dividing the plurality of gate electrode layers and connected to the cell array region and the connection region of the substrate, and a second metal line dividing a portion of the plurality of gate electrode layers and connected to the connection region of the substrate. A depth of a lower end portion of the second metal line may be greater than a depth of a lower end portion of the first metal line in the cell array region, based on an upper surface of the substrate.

Abstract: A hinge assembly of a computing device may be provided, for example. The hinge assembly may include a first hinge member and a second hinge member. The first hinge member may include a first mounting plate attached to a first gudgeon member via a first tongue portion. The second hinge member may include a second mounting plate attached to a second gudgeon member via a second tongue portion. The first and second mounting plates may be shaped so that they can be stacked in parallel along an axis such that the first and second gudgeons may be aligned perpendicular to the axis to allow a pintle member to be inserted through the first and second gudgeons and such that the first and second tongue portions may be spaced apart along the axis.

Abstract: A vertical memory device includes a substrate having a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, and forming a stepped structure in the connection region, a first metal line dividing the plurality of gate electrode layers and connected to the cell array region and the connection region of the substrate, and a second metal line dividing a portion of the plurality of gate electrode layers and connected to the connection region of the substrate. A depth of a lower end portion of the second metal line may be greater than a depth of a lower end portion of the first metal line in the cell array region, based on an upper surface of the substrate.

Abstract: An optical lens and a light emitting module having the optical lens is provided. The optical lens may include a bottom surface, a recess upwardly convex at a central region of the bottom surface, a light input surface at a circumference of the recess, a first light output surface having a convexly curved surface at opposite sides of the bottom surface and the light input surface, and a second light output surface at a lower circumference of the first light output surface, wherein the bottom surface includes a first edge adjacent to the recess and a second edge adjacent to the second light output surface, a region of the bottom surface more adjacent to the first edge gradually approaches a first axis that is horizontal to a center of a bottom of the recess, and the first light output surface has a convex central region.

Abstract: Disclosed is a three-dimensional semiconductor device including a stack structure on a substrate and including electrodes that are vertically stacked on top of each other on a first region of a substrate, a vertical structure penetrating the stack structure and including a first semiconductor pattern, a data storage layer between the first semiconductor pattern and at least one of the electrodes, a transistor on a second region of the substrate, and a first contact coupled to the transistor. The first contact includes a first portion and a second portion on the first portion. Each of the first portion and the second portions has a diameter that increases with an increasing vertical distance from the substrate. A diameter of an upper part of the first portion is greater than a diameter of a lower part of the second portion.

Abstract: In accordance with the present description, there is provided multiple embodiments of a semiconductor device. In each embodiment, the semiconductor device comprises a substrate having a conductive pattern formed thereon. In addition to the substrate, each embodiment of the semiconductor device includes at least one semiconductor die which is electrically connected to the substrate, both the semiconductor die and the substrate being at least partially covered by a package body of the semiconductor device. In certain embodiments of the semiconductor device, through-mold vias are formed in the package body to provide electrical signal paths from an exterior surface thereof to the conductive pattern of the substrate. In other embodiments, through mold vias are also included in the package body to provide electrical signal paths between the semiconductor die and an exterior surface of the package body.

Abstract: The present invention relates to an Al—Zn—Cu alloy comprising: 18 to 50 parts by weight of zinc; 0.05 to 5 parts by weight of copper; and the rest being aluminum, based on the total weight of the alloy, wherein a tensile strength is 230 to 450 MPa and an elongation is 2.75 to 10% in the cast state. According to the present invention, it is possible to provide an Al—Zn—Cu alloy having improved casting property, strength and elongation at the same time.

Abstract: A laser detector includes a latch and a semiconductor device including the same. The laser detector includes a latch configured to output an output signal and an inverted output signal and an initial value setting circuit configured to set an initial value of at least one of the output signal and the inverted output signal. The latch includes a first transistor controlled to be initially turned on by the initial value and a second transistor controlled to be initially turned off by the initial value. The second transistor has an active region having a lateral area that is greater than that of the first transistor.

Abstract: A semiconductor device for monitoring a reverse voltage is provided. The semiconductor device includes an intellectual property having an input node and an output node; a passive component connected between the output node and a potential; a monitoring circuit connected to the input node and the output node and powered by a driving power, the monitoring circuit monitoring a difference between an input level at the input node and an output level at the output node to detect a reverse voltage across the intellectual property. The driving power is provided by the output node.

Abstract: The present invention relates to a Ti-included oxide dispersion strengthened copper alloy and a method for preparing oxide dispersion copper by an internal oxidation Ti-included copper alloy, which thus allows spheronization and refinement of the oxides, and reduction of distance between the oxides. According to the present invention, there is provided oxide dispersion copper having excellent hardness and tensile strength as well as electrical conductivity by performing spheronization and refinement for Ti-included oxide and thus further reducing the distance between oxides.

Abstract: Various embodiments of the present disclosure provide an antenna device and/or an electronic device including the antenna device. The antenna device may include: a circuit board; a conductive layer disposed in a partial region of the circuit board; a first radiation conductor disposed at one side of the conductive layer on the circuit board; and second radiation conductors disposed at one side of the conductive layer on the circuit board, the second radiation conductors being respectively disposed at opposite sides of the first radiation conductor to be symmetrical to each other. The first radiation conductor may transmit or receive a wireless signal in a first frequency band, and the second radiation conductors may transmit or receive a wireless signal in a second frequency band that is different from the first frequency band.

Abstract: A thermoelectric element is provided as follows. First and second semiconductor fin structures are disposed on a semiconductor substrate. Each semiconductor fin structure extends in a first direction, protruding from the semiconductor substrate. First and second semiconductor nanowires are disposed on the first and second semiconductor fin structures, respectively. The first semiconductor nanowires include first impurities. The second semiconductor nanowires include second impurities different from the first impurities. A first electrode is connected to first ends of the first and second semiconductor nanowires. A second electrode is connected to second ends of the first semiconductor nanowires. A third electrode is connected to second ends of the second semiconductor nanowires.

Abstract: Systems and methods for reducing sensing time for sensing data states stored within a plurality of memory cells are described. In some cases, the ramping of a word line connected to the plurality of memory cells may be delayed until a threshold current corresponding with a particular number of erased memory cells of the plurality of memory cells has been met or exceeded. The threshold current may be compared with a summation of a first set of detection currents corresponding with a first set of memory cells of the plurality of memory cells that have been sensed to be in a conducting state while the word line is set to a voltage level for sensing erased memory cells. The threshold current may be set based on a chip temperature and/or a particular number of bit errors that occurred during a prior sensing operation.

Abstract: Disclosed is a semiconductor device having overlapped via apertures formed in an encapsulant to outwardly expose solder balls. When different types of semiconductor devices are electrically connected to the solder balls through the overlapped via apertures, flux or solder paste is unlikely to contact sidewall portions of the overlapped via apertures. Therefore, different types of semiconductor devices can be mounted with improved efficiency.

Abstract: A vertical memory device includes a channel, gate lines, and a cutting pattern, respectively, on a substrate. The channel extends in a first direction substantially perpendicular to an upper surface of the substrate. The gate linesare spaced apart from each other in the first direction. Each of the gate lines surrounds the channel and extends in a second direction substantially parallel to the upper surface of the substrate. The cutting pattern includes a first cutting portion extending in the first direction and cutting the gate lines, and a second cutting portion crossing the first cutting portion and merged with the first cutting portion.