Patents by Inventor Kwang Ho Kim

Kwang Ho Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Bad Column Management with Bit Information in Non-Volatile Memory Systems
    Publication number: 20140219023
    Abstract: Column based defect management techniques are presented. Each column of the memory has an associated isolation latch or register whose value indicates whether the column is defective, but in addition to this information, for columns marked as defective, additional information is used to indicate whether the column as a whole is to be treated as defective, or whether just individual bits of the column are defective. The defective elements can then be re-mapped to a redundant element at either the appropriate bit or column level based on the data. When a column is bad, but only on the bit level, the good bits can still be used for data, although this may be done at a penalty of under programming for some bits, as is described further below. A self contained Built In Self Test (BIST) flow constructed to collect the bit information through a set of column tests is also described.
    Type: Application
    Filed: April 3, 2014
    Publication date: August 7, 2014
    Applicant: SanDisk Technologies Inc.
    Inventors: Yan Li, Kwang-ho Kim, Frank Tsai, Aldo Bottelli
  • Bit line resistance compensation
    Patent number: 8743618
    Abstract: Methods for compensating for variations in bit line resistance during sensing of memory cells are described. The variations in bit line resistance may occur die-to-die or plane-to-plane on the same die. In some embodiments, for each die or memory plane on a die, a plurality of bit line read voltages associated with a plurality of zones may be determined based on sensing criteria. The sensing criteria may comprise a number of fail bits. Each zone of the plurality of zones may be associated with a memory array region within a die or memory plane. Prior to performing a read or verify operation on a group of memory cells, a bit line read voltage used during sensing of the group of memory cells may be determined based on the plurality of bit line read voltages and a zone associated with the group of memory cells.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: June 3, 2014
    Assignee: Sandisk Technologies Inc.
    Inventors: Teruhiko Kamei, Seungpil Lee, Siu Lung Chan, Kwang Ho Kim, Man Lung Mui
  • BIT LINE RESISTANCE COMPENSATION
    Publication number: 20140133231
    Abstract: Methods for compensating for variations in bit line resistance in non-volatile memories are described. In some embodiments, use of multiple patterning lithography for forming bit lines may lead to systematic variations in bit line resistance between groups of bit lines within a memory array. For example, in some cases, every fourth bit line of four neighboring (or adjacent) bit lines may be formed differently than the other three bit lines within a group of four neighboring bit lines. In one embodiment, bit line segment swapping may be used between blocks within a memory array in order to mitigate variations in bit line resistance. In another embodiment, each group of adjacent bit line segments may be offset (or staggered) per block such that the local routing necessary to connect bit line segments into bit lines may be simplified.
    Type: Application
    Filed: January 31, 2013
    Publication date: May 15, 2014
    Applicant: SANDISK TECHNOLOGIES, INC.
    Inventors: Kwang Ho Kim, Fumiaki Toyama, Seungpil Lee, Masaaki Higashitani
  • BIT LINE RESISTANCE COMPENSATION
    Publication number: 20140133230
    Abstract: Methods for compensating for variations in bit line resistance during sensing of memory cells are described. The variations in bit line resistance may occur die-to-die or plane-to-plane on the same die. In some embodiments, for each die or memory plane on a die, a plurality of bit line read voltages associated with a plurality of zones may be determined based on sensing criteria such as a number of fail bits. Each zone of the plurality of zones may be associated with a memory array region within a memory plane. Within each zone, different bit line read voltages may be applied to different bit line groupings in order to compensate for systematic variations in bit line resistance between neighboring bit lines due to the use of multiple patterning lithography techniques such as spacer-based double patterning.
    Type: Application
    Filed: January 31, 2013
    Publication date: May 15, 2014
    Applicant: SANDISK TECHNOLOGIES, INC.
    Inventors: Teruhiko Kamei, Seungpil Lee, Siu Lung Chan, Kwang Ho Kim, Man Lung Mui
  • BIT LINE RESISTANCE COMPENSATION
    Publication number: 20140133229
    Abstract: Methods for compensating for variations in bit line resistance during sensing of memory cells are described. The variations in bit line resistance may occur die-to-die or plane-to-plane on the same die. In some embodiments, for each die or memory plane on a die, a plurality of bit line read voltages associated with a plurality of zones may be determined based on sensing criteria. The sensing criteria may comprise a number of fail bits. Each zone of the plurality of zones may be associated with a memory array region within a die or memory plane. Prior to performing a read or verify operation on a group of memory cells, a bit line read voltage used during sensing of the group of memory cells may be determined based on the plurality of bit line read voltages and a zone associated with the group of memory cells.
    Type: Application
    Filed: January 31, 2013
    Publication date: May 15, 2014
    Applicant: SANDISK TECHNOLOGIES, INC.
    Inventors: Teruhiko Kamei, Seungpil Lee, Siu Lung Chan, Kwang Ho Kim, Man Lung Mui
  • System on chip, devices having the same, and method for power control of the SOC
    Patent number: 8726047
    Abstract: Disclosed is an integrated circuit device including a plurality of power domain blocks, which includes a core power domain block. A power control circuit is configured to control power supplied to each of the plurality of power domain blocks independently responsive to control communication from the core power domain block. The power control circuit includes a plurality of power clusters corresponding to the plurality of power domain blocks, respectively. The plurality of power clusters control power supplied to the plurality of power domain blocks, respectively, independently responsive to the control communication from the core power domain block.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: May 13, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae Gon Lee, Jang Ho Cho, Bong Il Park, Kwang Ho Kim, Taek Kyun Shin, Dong Keun Kim, Jae Young Lee, Yung Hei Lee
  • Bad column management with bit information in non-volatile memory systems
    Patent number: 8711625
    Abstract: Column based defect management techniques are presented. Each column of the memory has an associated isolation latch or register whose value indicates whether the column is defective, but in addition to this information, for columns marked as defective, additional information is used to indicate whether the column as a whole is to be treated as defective, or whether just individual bits of the column are defective. The defective elements can then be re-mapped to a redundant element at either the appropriate bit or column level based on the data. When a column is bad, but only on the bit level, the good bits can still be used for data.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: April 29, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Yan Li, Kwang-Ho Kim, Frank W. Tsai, Aldo Bottelli
  • Compact sense amplifier for non-volatile memory suitable for quick pass write
    Patent number: 8705293
    Abstract: A compact and versatile sense amp is presented. Among its other features this sense amp arrangement provides a way to pre-charge bit lines while doing data scanning. Another feature is that the sense amp circuit can provide a way to set three different bit line levels used in the quick pass write (QPW) technique using dynamic latch, where quick pass write is a technique where cells along a given word line selected for programming can be enabled, inhibited, or partially inhibited for programming. Also, it can provide a convenient way to measure the cell current.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: April 22, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Min She, Yan Li, Kwang-Ho Kim, Siu Lung Chan
  • Data storage device and method performing background operation with selected data compression
    Patent number: 8706953
    Abstract: A method of storing data in a storage medium of a data storage device comprises storing input data in the storage medium, and reading the input data from the storage medium and compressing the read data during a background operation of the data storage device.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: April 22, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung Lae Cho, Kwang Ho Kim, Jun Jin Kong, Jaehong Kim, Hong Rak Son
  • METHOD FOR PRODUCING METAL CATALYST FOR PREPARING ALCOHOL AND METAL CATALYST PRODUCED THEREBY
    Publication number: 20140106959
    Abstract: Disclosed is a method for preparing a metal catalyst having improved yield of alcohols. The method for preparing a metal catalyst for the production of alcohol from synthesis gas includes forming a metal catalyst; and irradiating the metal catalyst with gamma rays. The metal catalyst has improved yield of alcohols by stabilizing the metal catalyst through gamma ray irradiation to inhibit generation of hydrocarbons in catalytic reaction with synthesis gas.
    Type: Application
    Filed: October 8, 2013
    Publication date: April 17, 2014
    Applicant: Korea Institute of Energy Research
    Inventors: Sun-Hwa YEON, Dae-Hyun SHIN, Nam-Sun NHO, Kyoung-Hee SHIN, Chang-Soo JIN, Sung-Chan NAM, Je-Kyoung WOO, Kwang-Ho KIM
  • METHOD AND ELECTRONIC DEVICE FOR RUNNING APPLICATION
    Publication number: 20140096083
    Abstract: A method and an electronic device run an application. The method for running an application in an electronic device includes displaying one application icon of one or more applications contained in a folder, in an icon of the folder, detecting a gesture to the folder icon, and running or changing the application displayed in the folder icon according to the gesture to the folder icon.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 3, 2014
    Applicant: Samsung Electronics Co., Ltd
    Inventors: Kwang-Ho Kim, Tae-Gun Park
  • OPTICAL LENS, LIGHT EMITTING DEVICE, AND LIGHTING DEVICE HAVING THE SAME
    Publication number: 20140061699
    Abstract: The light emitting device includes a light emitting chip, and an optical lens provided over the light emitting chip. The optical lens includes an incident surface into which a light emitted from the light emitting chip is incident, a recess portion opposite to the incident surface and recessed in a direction of the incident surface, an exit surface provided at a peripheral portion of the recess portion to output a light incident through the incident surface, and a convex portion protruding between the recess portion and the exit surface and connected with at least one of the recess portion and the exit surface through an inflection point. The convex portion is located inward of a line segment ranging from the light emitting chip to a first inflection point provided at an outermost portion of the recess portion.
    Type: Application
    Filed: August 6, 2013
    Publication date: March 6, 2014
    Inventor: Kwang Ho KIM
  • Circulatory photobioreactor
    Patent number: 8658421
    Abstract: A circulatory photobioreactor is provided. The circulatory photobioreactor comprises a first cultivating part, a second cultivating part and a pump part connecting the first cultivating part and the second cultivating part. The first cultivating part comprises a culture tank in which culture media are supplied and a first light source coupled to the culture tank, which illuminates the inside of the culture tank. The second cultivating part comprises a culture pipe placed outside of the culture tank and supplied with cultures from the culture tank and a second light source coupled to the culture pipe, which illuminates the inside of the culture pipe. The pump part is connected to both the first cultivating part and the second cultivating part in order to circulate the culture solution between them.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: February 25, 2014
    Assignees: Kairos Global Co., Ltd., Eulgi University Industry Academy Cooperation Foundation
    Inventors: Kwang Ho Kim, Hee-Gyoo Kang, Young Il Kwon, Sun Jong Kim, Hee Joung Lim, Mi Jeong Kim
  • Compact sense amplifier for non-volatile memory
    Patent number: 8630120
    Abstract: A compact and versatile sense amp is presented. Among its other features this sense amp arrangement provides a way to pre-charge bit lines while doing data scanning. Another feature is that the sense amp circuit can provide a way to set three different bit line levels used in the quick pass write (QPW) technique using dynamic latch, where quick pass write is a technique where cells along a given word line selected for programming can be enabled, inhibited, or partially inhibited for programming. Also, it can provide a convenient way to measure the cell current.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: January 14, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Min She, Yan Li, Kwang-Ho Kim, Siu Lung Chan
  • BIT LINE BL ISOLATION SCHEME DURING ERASE OPERATION FOR NON-VOLATILE STORAGE
    Publication number: 20130301358
    Abstract: A system for erasing non-volatile storage system that reduces the voltage across the transistor that interfaces between the sense amplifier and the bit line so that the transistor can be made smaller. Additionally, the use of the lower voltage allows for various components to be positioned closer to each other. The use of smaller components and smaller spaces between components allows the non-volatile storage system to include more memory cells, thereby providing the ability to store more data.
    Type: Application
    Filed: May 3, 2013
    Publication date: November 14, 2013
    Applicant: SANDISK TECHNOLOGIES, INC.
    Inventors: Mohan Vamsi Dunga, Kwang-Ho Kim, Masaaki Higashitani
  • Semiconductor device having overlapped via apertures
    Patent number: 8557629
    Abstract: Disclosed is a semiconductor device having overlapped via apertures formed in an encapsulant to outwardly expose solder balls. When different types of semiconductor devices are electrically connected to the solder balls through the overlapped via apertures, flux or solder paste is unlikely to contact sidewall portions of the overlapped via apertures. Therefore, different types of semiconductor devices can be mounted with improved efficiency.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: October 15, 2013
    Assignee: Amkor Technology, Inc.
    Inventors: Jin Seong Kim, Dong Joo Park, Kwang Ho Kim, Hee Yeoul Yoo, Jeong Wung Jeong
  • LDO regulator and semiconductor device including the same
    Patent number: 8536845
    Abstract: In a low drop out (LDO) regulator and a semiconductor device including the LDO regulator, the LDO regulator regulates a power supply voltage and applies the regulated power supply voltage to a load. The LDO regulator comprises: an output node connected to the load; a pass transistor that applies a power supply voltage to the output node; and a controller that generates a load enable signal enabling the load by delaying a regulator enable signal by a first delay time, and that increases a gate voltage of the pass transistor after receiving the regulator enable signal to thereby reduce a current flowing through the pass transistor.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: September 17, 2013
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Kwang-ho Kim, Jin-hyuk Jeung
  • Semiconductor device and fabricating method thereof
    Patent number: 8525318
    Abstract: Disclosed are a semiconductor device capable of efficiently radiating heat of a semiconductor die and a method of fabricating the same. The semiconductor device efficiently radiates the heat by preventing an encapsulant from reaching the semiconductor die by an encapsulant dam so that an upper surface of the semiconductor die is exposed out of the encapsulant. In addition, the semiconductor device is configured to expose a pre-solder ball or a conductive pattern of a substrate through a via of the encapsulant. Therefore, electrical connection between the pre-solder ball and a solder ball of another semiconductor device stacked thereon is easily achieved.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: September 3, 2013
    Assignee: Amkor Technology, Inc.
    Inventors: Jin Seong Kim, Dong Joo Park, Kwang Ho Kim, Ye Sul Ahn
  • Compact Sense Amplifier for Non-Volatile Memory Suitable for Quick Pass Write
    Publication number: 20130100740
    Abstract: A compact and versatile sense amp is presented. Among its other features this sense amp arrangement provides a way to pre-charge bit lines while doing data scanning. Another feature is that the sense amp circuit can provide a way to set three different bit line levels used in the quick pass write (QPW) technique using dynamic latch, where quick pass write is a technique where cells along a given word line selected for programming can be enabled, inhibited, or partially inhibited for programming. Also, it can provide a convenient way to measure the cell current.
    Type: Application
    Filed: October 20, 2011
    Publication date: April 25, 2013
    Inventors: Min She, Yan Li, Kwang-Ho Kim, Siu Lung Chan
  • Compact Sense Amplifier for Non-Volatile Memory
    Publication number: 20130100744
    Abstract: A compact and versatile sense amp is presented. Among its other features this sense amp arrangement provides a way to pre-charge bit lines while doing data scanning. Another feature is that the sense amp circuit can provide a way to set three different bit line levels used in the quick pass write (QPW) technique using dynamic latch, where quick pass write is a technique where cells along a given word line selected for programming can be enabled, inhibited, or partially inhibited for programming. Also, it can provide a convenient way to measure the cell current.
    Type: Application
    Filed: October 20, 2011
    Publication date: April 25, 2013
    Inventors: Min She, Yan Li, Kwang-Ho Kim, Siu Lung Chan