Patents by Inventor Kwang Ho Kim

Kwang Ho Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Bad column management with bit information in non-volatile memory systems
    Patent number: 9748001
    Abstract: Column based defect management techniques are presented. Each column of the memory has an associated isolation latch or register whose value indicates whether the column is defective, but in addition to this information, for columns marked as defective, additional information is used to indicate whether the column as a whole is to be treated as defective, or whether just individual bits of the column are defective. The defective elements can then be re-mapped to a redundant element at either the appropriate bit or column level based on the data. When a column is bad, but only on the bit level, the good bits can still be used for data, although this may be done at a penalty of under programming for some bits, as is described further below. A self contained Built In Self Test (BIST) flow constructed to collect the bit information through a set of column tests is also described.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: August 29, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Yan Li, Kwang-ho Kim, Frank Tsai, Aldo Bottelli
  • Memory device which performs verify operations using different sense node pre-charge voltages and a common discharge period
    Patent number: 9721671
    Abstract: Sense circuits in a memory device can be pre-charged to different levels in a sensing process to reduce the amount of time used for sensing. During sensing of first and second memory cells, a control circuit pre-charges first and second sense circuits to first and second voltages, respectively. The first and second sense circuits are associated with the first and second memory cells, respectively. Also, during the sensing, a control gate voltage is applied to the first and second memory cells. The control circuit allows the first and second sense node voltages to discharge in a common discharge period and the cells are sensed using a common trip condition. The first and second memory cells are therefore subject to different concurrent verify tests.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: August 1, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Alexander Chu, Jong Hak Yuh, Kwang-Ho Kim, Yenlung Li, Farookh Moogat
  • Method for evaluating fracture toughness using instrumented indentation testing
    Patent number: 9702798
    Abstract: The present invention relates to a method for measuring a fracture toughness using an instrumented indentation testing, which measures a load and an indentation depth in real time while applying a load to a specimen by an indenter having a flat punch shape.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: July 11, 2017
    Assignee: FRONTICS, INC.
    Inventors: Jun Yeong Kim, Dong Il Kwon, Kwang Ho Kim, Seung Won Jeon, Woo Joo Kim, Seung Hun Choi
  • Hinge assemblies for computing devices
    Patent number: 9703328
    Abstract: A hinge assembly of a computing device may be provided, for example. The hinge assembly may include a first hinge member and a second hinge member. The first hinge member may include a first mounting plate attached to a first gudgeon member via a first tongue portion. The second hinge member may include a second mounting plate attached to a second gudgeon member via a second tongue portion. The first and second mounting plates may be shaped so that they can be stacked in parallel along an axis such that the first and second gudgeons may be aligned perpendicular to the axis to allow a pintle member to be inserted through the first and second gudgeons and such that the first and second tongue portions may be spaced apart along the axis.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: July 11, 2017
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Kwang Ho Kim
  • LENS AND LIGHT-EMITTING DEVICE MODULE COMPRISING THE SAME
    Publication number: 20170114979
    Abstract: An embodiment provides a lens for changing the path of light incident from a light source, the lens comprising: region 1 which faces a light source and has a concave section formed thereon; and region 2 which faces region 1 and has a central region concave in the direction of region 1, wherein the surface of the concave section comprises: region 1-1 facing the center of the light source; region 1-3 formed at the edge; and region 1-2 formed between region 1-1 and region 1-3, the curvatures of region 1-1, region 1-2 and region 1-3 being different from one another.
    Type: Application
    Filed: March 24, 2015
    Publication date: April 27, 2017
    Applicant: LG INNOTEK CO., LTD.
    Inventors: Min Soo KANG, Kwang Ho KIM
  • SEMICONDUCTOR DEVICE WITH THROUGH-MOLD VIA
    Publication number: 20170117214
    Abstract: In accordance with the present invention, there is provided multiple embodiments of a semiconductor device. In each embodiment, the semiconductor device comprises a substrate having a conductive pattern formed thereon. In addition to the substrate, each embodiment of the semiconductor device includes at least one semiconductor die which is electrically connected to the substrate, both the semiconductor die and the substrate being at least partially covered by a package body of the semiconductor device. In certain embodiments of the semiconductor device, through-mold vias are formed in the package body to provide electrical signal paths from an exterior surface thereof to the conductive pattern of the substrate. In other embodiments, through mold vias are also included in the package body to provide electrical signal paths between the semiconductor die and an exterior surface of the package body.
    Type: Application
    Filed: December 26, 2016
    Publication date: April 27, 2017
    Applicant: AMKOR TECHNOLOGY, INC.
    Inventors: Dong Joo PARK, Jin Seong KIM, Ki Wook LEE, Dae Byoung KANG, Ho CHOI, Kwang Ho KIM, Jae Dong KIM, Yeon Soo JUNG, Sung Hwan CHO
  • Auxiliary power supply and user device including the same
    Patent number: 9626259
    Abstract: A user device is provided. The device includes a main power supply, and an auxiliary power supply. The main power supply provides a main power. The auxiliary power supply cuts off the main power according to a power level of the main power supply and provides an auxiliary power upon Sudden Power-Off (SPO).
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: April 18, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hwan-Jin Yong, Donghyun Song, Janghwan Kim, Young-Goo Ko, Hyuck-Sun Kwon, Taek-Sung Kim, Kwang-Ho Kim, Byungjin Ahn, Dongjin Lee, Byungse So, Jong-Gyu Park, Kyoungsub Oh, Kwan-Jong Park, Jong-Soo Seo, Tae-Hwa Yoo, Min-Ho Kim
  • Optical lens, light emitting device, and lighting device having the same
    Patent number: 9625118
    Abstract: Disclosed is an optical lens. The optical lens includes a bottom surface having a recess part at center thereof; a light exit surface provided in opposite to the bottom surface and having a convex curved surface; an outer sidewall connected between the bottom surface and the light exit surface; a recess portion recessed toward the bottom surface; and a convex portion provided between the recess portion and the light exit surface. The recess part is convexly recessed in a direction of the recess portion. The recess portion includes a first to third total-reflection surface having curvatures different from each other. The convex portion is protruded inwardly from an inflection point between the convex portion and the light exit surface.
    Type: Grant
    Filed: November 27, 2015
    Date of Patent: April 18, 2017
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Kwang Ho Kim
  • Verify Operations Using Different Sense Node Voltages In A Memory Device
    Publication number: 20170076812
    Abstract: Sense circuits in a memory device can be pre-charged to different levels in a sensing process to reduce the amount of time used for sensing. For example, in a program operation, a memory cell is in a fast programming mode until its threshold voltage exceeds an offset verify voltage (VO) of a data state. The offset verify voltage is below a final verify voltage (VF) of the data state. When the threshold voltage is between VO and VF, the memory cell is in a slow programming mode. A verify test at VO for one memory cell can be performed concurrently with a verify test at VF for another memory cell by pre-charging a sense circuit for the one memory cell to a higher voltage than a sense circuit for the another memory cell. A common discharge period and trip condition can be used.
    Type: Application
    Filed: September 10, 2015
    Publication date: March 16, 2017
    Applicant: SanDisk Technologies Inc.
    Inventors: Alexander Chu, Jong Hak Yuh, Kwang-Ho Kim, Yenlung Li, Farookh Moogat
  • Method for producing metal catalyst for preparing alcohol and metal catalyst produced thereby
    Patent number: 9579634
    Abstract: Disclosed is a method for preparing a metal catalyst having improved yield of alcohols. The method for preparing a metal catalyst for the production of alcohol from synthesis gas includes forming a metal catalyst; and irradiating the metal catalyst with gamma rays. The metal catalyst has improved yield of alcohols by stabilizing the metal catalyst through gamma ray irradiation to inhibit generation of hydrocarbons in catalytic reaction with synthesis gas.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: February 28, 2017
    Assignee: Korea Institute of Energy Research
    Inventors: Sun-Hwa Yeon, Dae-Hyun Shin, Nam-Sun Nho, Kyoung-Hee Shin, Chang-Soo Jin, Sung-Chan Nam, Je-Kyoung Woo, Kwang-Ho Kim
  • SEMICONDUCTOR DEVICE HAVING A MISMATCH DETECTION AND CORRECTION CIRCUIT
    Publication number: 20170023966
    Abstract: A semiconductor device includes: an integrated circuit (IC) including an internal circuit; and a mismatch detection and correction circuit connected to the internal circuit of the IC, the mismatch detection and correction circuit configured to detect a process mismatch and correct an error in the internal circuit caused by the process mismatch using a current difference between a first current and a second current based on a charged voltage of a capacitor.
    Type: Application
    Filed: May 27, 2016
    Publication date: January 26, 2017
    Inventors: JOO-SEONG KIM, Sang-Ho Kim, Kwang-Ho Kim
  • Sense amplifier with efficient use of data latches
    Patent number: 9552882
    Abstract: A non-volatile memory includes an data latch structure for programming bit lines using at least three programming levels. A sense amplifier includes a first data latch for controlling the voltage of a corresponding bit line, and a second static data latch with scan circuitry for performing logic operations on the program data and sense results. The sense amplifier scans low verify sense results with program data to generate reduced programming data. The reduced programming data is transferred out of the first data latch after sensing for all states and the program data is scanned to generate program enable/inhibit data which is stored in the first data latch. After setting the bit line to a program inhibit or program enable level, the reduced programming data is transferred back to the first data latch. The bit lines for reduced programming are then adjusted to the reduced programming level.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: January 24, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Tai-Yuan Tseng, Yenlung Li, Cynthia Hsu, Kwang Ho Kim, Man L Mui
  • FAST SCAN TO DETECT BIT LINE DISCHARGE TIME
    Publication number: 20160372200
    Abstract: Systems and methods for reducing sensing time for sensing data states stored within a plurality of memory cells are described. In some cases, the ramping of a word line connected to the plurality of memory cells may be delayed until a threshold current corresponding with a particular number of erased memory cells of the plurality of memory cells has been met or exceeded. The threshold current may be compared with a summation of a first set of detection currents corresponding with a first set of memory cells of the plurality of memory cells that have been sensed to be in a conducting state while the word line is set to a voltage level for sensing erased memory cells. The threshold current may be set based on a chip temperature and/or a particular number of bit errors that occurred during a prior sensing operation.
    Type: Application
    Filed: June 16, 2016
    Publication date: December 22, 2016
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Yen-Lung Li, Jong Yuh, Jonathan Huynh, Tai-Yuan Tseng, Kwang-Ho Kim, Qui Nguyen
  • Fabrication method of DLC/Ti electrode with multi-interface layers for water treatment
    Publication number: 20160351290
    Abstract: In this layer, the Ti:N, Ti:C:N sublayer is formed on the etched Ti substrate, and DLC is coated, and afterwards, the proportion of the sp2 carbon structure and the sp3 carbon structure is changed to lower the surface specific resistance, and by having electrochemical traits, the trait of enhancing the adhesion of the Ti substrate and the DLC layer is caused to have high durability and electrochemical traits, providing wide-area water-treatment DLC/Ti electrode manufacture method.
    Type: Application
    Filed: December 27, 2015
    Publication date: December 1, 2016
    Applicant: Hybrid Interface Materials
    Inventor: Kwang Ho Kim
  • State-dependent lockout in non-volatile memory
    Patent number: 9437302
    Abstract: A sense amplifier provides a state-dependent lockout to limit sensing to those bit lines that target a currently selected state for sensing. A sense amplifier scans program data prior to sensing at the verify levels corresponding to a plurality of states. When program data matches a currently selected state, the sense amplifier senses the bit line voltage during verification and writes the result to a data latch. The sense amplifier may write the result to a data latch for storing quick pass write data, in response to sensing at a low verify level for the selected state for example. When program data does not match the currently selected state, the sense amplifier skips sensing for the bit line. The sense amplifier locks out the bit line prior to sensing based on the program data.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: September 6, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Tai-Yuan Tseng, Cynthia Hsu, Kwang Ho Kim
  • LASER DETECTOR USING LATCH AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
    Publication number: 20160225725
    Abstract: A laser detector includes a latch and a semiconductor device including the same. The laser detector includes a latch configured to output an output signal and an inverted output signal and an initial value setting circuit configured to set an initial value of at least one of the output signal and the inverted output signal. The latch includes a first transistor controlled to be initially turned on by the initial value and a second transistor controlled to be initially turned off by the initial value. The second transistor has an active region having a lateral area that is greater than that of the first transistor.
    Type: Application
    Filed: January 29, 2016
    Publication date: August 4, 2016
    Inventors: Kwang Ho Kim, Sang Ho Kim
  • SOLAR CELL HAVING QUANTUM WELL STRUCTURE AND METHOD FOR MANUFACTURING SAME
    Publication number: 20160204291
    Abstract: The present invention provides a practical solar cell having a multiple quantum well structure and a method for manufacturing the same, and the heterostructure solar cell is capable of reducing the transmission loss of solar light and the short wavelength loss of solar light by inserting a multi-layer quantum well structure between p- and n-type semiconductors, thereby obtaining a high-efficiency solar cell which can overcome the limitations of theoretical conversion efficiency and reducing manufacturing costs.
    Type: Application
    Filed: June 5, 2013
    Publication date: July 14, 2016
    Inventor: Kwang-Ho KIM
  • OPTICAL LENS, LIGHT EMITTING MODULE AND LIGHT UNIT HAVING THE SAME
    Publication number: 20160201875
    Abstract: An optical lens and a light emitting module having the optical lens is provided. The optical lens may include a bottom surface, a recess upwardly convex at a central region of the bottom surface, a light input surface at a circumference of the recess, a first light output surface having a convexly curved surface at opposite sides of the bottom surface and the light input surface, and a second light output surface at a lower circumference of the first light output surface, wherein the bottom surface includes a first edge adjacent to the recess and a second edge adjacent to the second light output surface, a region of the bottom surface more adjacent to the first edge gradually approaches a first axis that is horizontal to a center of a bottom of the recess, and the first light output surface has a convex central region.
    Type: Application
    Filed: January 8, 2016
    Publication date: July 14, 2016
    Inventors: Min Soo KANG, Kwang Ho KIM, Yun Ho SHIN, Sun Woong KIM, Ui Youn JUNG
  • Ti-INCLUDED OXIDE DISPERSION STRENGTHENED COPPER ALLOY AND METHOD FOR MANUFACTURING DISPERSED COPPER
    Publication number: 20160189820
    Abstract: The present invention relates to a Ti-included oxide dispersion strengthened copper alloy and a method for preparing oxide dispersion copper by an internal oxidation Ti-included copper alloy, which thus allows spheronization and refinement of the oxides, and reduction of distance between the oxides. According to the present invention, there is provided oxide dispersion copper having excellent hardness and tensile strength as well as electrical conductivity by performing spheronization and refinement for Ti-included oxide and thus further reducing the distance between oxides.
    Type: Application
    Filed: April 23, 2015
    Publication date: June 30, 2016
    Inventors: Seung Zeon Han, Hong Rae Joh, Jee Hyuk Ahn, Kwang Ho Kim
  • Semiconductor storage device and method of throttling performance of the same
    Patent number: 9348521
    Abstract: A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device; and a controller configured to receive a write command from a host and program write data received from the host to the non-volatile memory device in response to the write command. The controller inserts idle time after receiving the write data from the host and/or after programming the write data to the non-volatile memory device.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: May 24, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-Bin Yoon, Yeong-jae Woo, Dong-gi Lee, Kwang-Ho Kim, Hyuck-Sun Kwon