Patents by Inventor Kwang Ho Kim

Kwang Ho Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor storage device and method of throttling performance of the same
    Patent number: 9348521
    Abstract: A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device; and a controller configured to receive a write command from a host and program write data received from the host to the non-volatile memory device in response to the write command. The controller inserts idle time after receiving the write data from the host and/or after programming the write data to the non-volatile memory device.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: May 24, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-Bin Yoon, Yeong-jae Woo, Dong-gi Lee, Kwang-Ho Kim, Hyuck-Sun Kwon
  • HINGE ASSEMBLIES FOR COMPUTING DEVICES
    Publication number: 20160109909
    Abstract: A hinge assembly of a computing device may be provided, for example. The hinge assembly may include a first hinge member and a second hinge member. The first hinge member may include a first mounting plate attached to a first gudgeon member via a first tongue portion. The second hinge member may include a second mounting plate attached to a second gudgeon member via a second tongue portion. The first and second mounting plates may be shaped so that they can be stacked in parallel along an axis such that the first and second gudgeons may be aligned perpendicular to the axis to allow a pintle member to be inserted through the first and second gudgeons and such that the first and second tongue portions may be spaced apart along the axis.
    Type: Application
    Filed: July 8, 2013
    Publication date: April 21, 2016
    Inventor: KWANG HO KIM
  • OPTICAL LENS, LIGHT EMITTING DEVICE, AND LIGHTING DEVICE HAVING THE SAME
    Publication number: 20160076732
    Abstract: Disclosed is an optical lens. The optical lens includes a bottom surface having a recess part at center thereof; a light exit surface provided in opposite to the bottom surface and having a convex curved surface; an outer sidewall connected between the bottom surface and the light exit surface; a recess portion recessed toward the bottom surface; and a convex portion provided between the recess portion and the light exit surface. The recess part is convexly recessed in a direction of the recess portion. The recess portion includes a first to third total-reflection surface having curvatures different from each other. The convex portion is protruded inwardly from an inflection point between the convex portion and the light exit surface.
    Type: Application
    Filed: November 27, 2015
    Publication date: March 17, 2016
    Inventor: Kwang Ho KIM
  • THERMOELECTRIC ELEMENT, METHOD OF MANUFACTURING THE SAME AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
    Publication number: 20160027986
    Abstract: A thermoelectric element is provided as follows. First and second semiconductor fin structures are disposed on a semiconductor substrate. Each semiconductor fin structure extends in a first direction, protruding from the semiconductor substrate. First and second semiconductor nanowires are disposed on the first and second semiconductor fin structures, respectively. The first semiconductor nanowires include first impurities. The second semiconductor nanowires include second impurities different from the first impurities. A first electrode is connected to first ends of the first and second semiconductor nanowires. A second electrode is connected to second ends of the first semiconductor nanowires. A third electrode is connected to second ends of the second semiconductor nanowires.
    Type: Application
    Filed: June 16, 2015
    Publication date: January 28, 2016
    Inventors: KWANG-HO KIM, Jun-Hyeok YANG, Hyung-Jong KO, Se-Ki KIM, Ho-Jin PARK, Se-Ra AN
  • Optical lens, light emitting device, and lighting device having the same
    Patent number: 9236543
    Abstract: The light emitting device includes a light emitting chip, and an optical lens provided over the light emitting chip. The optical lens includes an incident surface into which a light emitted from the light emitting chip is incident, a recess portion opposite to the incident surface and recessed in a direction of the incident surface, an exit surface provided at a peripheral portion of the recess portion to output a light incident through the incident surface, and a convex portion protruding between the recess portion and the exit surface and connected with at least one of the recess portion and the exit surface through an inflection point. The convex portion is located inward of a line segment ranging from the light emitting chip to a first inflection point provided at an outermost portion of the recess portion.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: January 12, 2016
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Kwang Ho Kim
  • Latch system
    Patent number: 9223355
    Abstract: A latch system employs momentum exchange impact damping. A latch is slideably arranged within a housing so that the latch can slide between a latch position and a release position. A damper spring urges a damper against a wedge of the latch. When a mechanical impact urges said latch toward the release position, the latch wedge impacts the damper so as to exchange momentum from the latch to the damper so that the latch remains in the latch position.
    Type: Grant
    Filed: February 28, 2009
    Date of Patent: December 29, 2015
    Assignee: Hewlett-Packard Development Company L.P.
    Inventor: Kwang Ho Kim
  • Semiconductor device having overlapped via apertures
    Patent number: 9177932
    Abstract: Disclosed is a semiconductor device having overlapped via apertures formed in an encapsulant to outwardly expose solder balls. When different types of semiconductor devices are electrically connected to the solder balls through the overlapped via apertures, flux or solder paste is unlikely to contact sidewall portions of the overlapped via apertures. Therefore, different types of semiconductor devices can be mounted with improved efficiency.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: November 3, 2015
    Inventors: Jin Seong Kim, Dong Joo Park, Kwang Ho Kim, Hee Yeoul Yoo, Jeong Wung Jeong
  • VEHICLE DIAGNOSIS SYSTEM
    Publication number: 20150310677
    Abstract: Disclosed is a vehicle diagnosis system including: a signal-collecting unit disposed at a proper place of the vehicle including CAN(Controller Area Network) communication modules which send a CAN signal to and receive it from a vehicle ECU for controlling states of all parts of the vehicle by a computer, through a CAN and which output an analog signal to a driver driven by the module according to a command from the vehicle ECU, wherein the signal-collecting unit synchronizes and collects the CAN signal and the analog signal at predetermined time intervals; and a diagnosing unit which detects changes of the CAN signal and the analog signal collected in the signal-collecting unit at synchronization collection periods, and if the change of any one of the two signals has not been detected, diagnoses that the CAN communication module outputting the relevant CAN signal and analog signal failed.
    Type: Application
    Filed: April 28, 2015
    Publication date: October 29, 2015
    Inventors: Ji Soo SHIN, Byoung Seoung Kang, Kwang Ho Kim, Hyuk Kim
  • State-Dependent Lockout In Non-Volatile Memory
    Publication number: 20150221391
    Abstract: A sense amplifier provides a state-dependent lockout to limit sensing to those bit lines that target a currently selected state for sensing. A sense amplifier scans program data prior to sensing at the verify levels corresponding to a plurality of states. When program data matches a currently selected state, the sense amplifier senses the bit line voltage during verification and writes the result to a data latch. The sense amplifier may write the result to a data latch for storing quick pass write data, in response to sensing at a low verify level for the selected state for example. When program data does not match the currently selected state, the sense amplifier skips sensing for the bit line. The sense amplifier locks out the bit line prior to sensing based on the program data.
    Type: Application
    Filed: February 6, 2015
    Publication date: August 6, 2015
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Tai-Yuan Tseng, Cynthia Hsu, Kwang Ho Kim
  • Sense Amplifier With Efficient Use Of Data Latches
    Publication number: 20150221348
    Abstract: A non-volatile memory includes an efficient data latch structure for programming bit lines using at least three programming levels. A sense amplifier includes a first data latch for controlling the voltage of a corresponding bit line, and a second static data latch with scan circuitry for performing logic operations on the program data and sense results. The sense amplifier scans low verify sense results with program data to generate reduced programming data. The reduced programming data is transferred out of the first data latch after sensing for all states and the program data is scanned to generate program enable/inhibit data which is stored in the first data latch. After setting the bit line to a program inhibit or program enable level, the reduced programming data is transferred back to the first data latch. The bit lines for reduced programming are then adjusted to the reduced programming level.
    Type: Application
    Filed: February 6, 2015
    Publication date: August 6, 2015
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Tai-Yuan Tseng, Yenlung Li, Cynthia Hsu, Kwang Ho Kim, Man L. Mui
  • Bit line resistance compensation
    Patent number: 9047954
    Abstract: Methods for compensating for variations in bit line resistance during sensing of memory cells are described. The variations in bit line resistance may occur die-to-die or plane-to-plane on the same die. In some embodiments, for each die or memory plane on a die, a plurality of bit line read voltages associated with a plurality of zones may be determined based on sensing criteria. The sensing criteria may comprise a number of fail bits. Each zone of the plurality of zones may be associated with a memory array region within a die or memory plane. Prior to performing a read or verify operation on a group of memory cells, a bit line read voltage used during sensing of the group of memory cells may be determined based on the plurality of bit line read voltages and a zone associated with the group of memory cells.
    Type: Grant
    Filed: April 19, 2014
    Date of Patent: June 2, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Teruhiko Kamei, Seungpil Lee, Siu Lung Chan, Kwang Ho Kim, Man Lung Mui
  • Bit line resistance compensation
    Patent number: 8988917
    Abstract: Methods for compensating for variations in bit line resistance in non-volatile memories are described. In some embodiments, use of multiple patterning lithography for forming bit lines may lead to systematic variations in bit line resistance between groups of bit lines within a memory array. For example, in some cases, every fourth bit line of four neighboring (or adjacent) bit lines may be formed differently than the other three bit lines within a group of four neighboring bit lines. In one embodiment, bit line segment swapping may be used between blocks within a memory array in order to mitigate variations in bit line resistance. In another embodiment, each group of adjacent bit line segments may be offset (or staggered) per block such that the local routing necessary to connect bit line segments into bit lines may be simplified.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: March 24, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Kwang Ho Kim, Fumiaki Toyama, Seungpil Lee, Masaaki Higashitani
  • AUXILIARY POWER SUPPLY AND USER DEVICE INCLUDING THE SAME
    Publication number: 20150026516
    Abstract: A user device is provided. The device includes a main power supply, and an auxiliary power supply. The main power supply provides a main power. The auxiliary power supply cuts off the main power according to a power level of the main power supply and provides an auxiliary power upon Sudden Power-Off (SPO).
    Type: Application
    Filed: July 22, 2014
    Publication date: January 22, 2015
    Inventors: Hwan-Jin YONG, Donghyun SONG, Janghwan KIM, Young-Goo KO, Hyuck-Sun KWON, Taek-Sung KIM, Kwang-Ho KIM, Byungjin AHN, Dongjin LEE, Byungse SO, Jong-Gyu PARK, Kyoungsub OH, Kwan-Jong PARK, Jong-Soo SEO, Tae-Hwa YOO, Min-Ho KIM
  • Bit line BL isolation scheme during erase operation for non-volatile storage
    Patent number: 8937837
    Abstract: A system for erasing non-volatile storage system that reduces the voltage across the transistor that interfaces between the sense amplifier and the bit line so that the transistor can be made smaller. Additionally, the use of the lower voltage allows for various components to be positioned closer to each other. The use of smaller components and smaller spaces between components allows the non-volatile storage system to include more memory cells, thereby providing the ability to store more data.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: January 20, 2015
    Assignee: Sandisk Technologies Inc.
    Inventors: Mohan Vamsi Dunga, Kwang-Ho Kim, Masaaki Higashitani
  • SEMICONDUCTOR STORAGE DEVICE AND METHOD OF THROTTLING PERFORMANCE OF THE SAME
    Publication number: 20150019801
    Abstract: A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device; and a controller configured to receive a write command from a host and program write data received from the host to the non-volatile memory device in response to the write command. The controller inserts idle time after receiving the write data from the host and/or after programming the write data to the non-volatile memory device.
    Type: Application
    Filed: October 2, 2014
    Publication date: January 15, 2015
    Inventors: Han Bin YOON, Yeong-Jae WOO, Dong Gi LEE, Kwang Ho KIM, Hyuck-Sun KWON
  • Bit line resistance compensation
    Patent number: 8908432
    Abstract: Methods for compensating for variations in bit line resistance during sensing of memory cells are described. The variations in bit line resistance may occur die-to-die or plane-to-plane on the same die. In some embodiments, for each die or memory plane on a die, a plurality of bit line read voltages associated with a plurality of zones may be determined based on sensing criteria such as a number of fail bits. Each zone of the plurality of zones may be associated with a memory array region within a memory plane. Within each zone, different bit line read voltages may be applied to different bit line groupings in order to compensate for systematic variations in bit line resistance between neighboring bit lines due to the use of multiple patterning lithography techniques such as spacer-based double patterning.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: December 9, 2014
    Assignee: Sandisk Technologies, Inc.
    Inventors: Teruhiko Kamei, Seungpil Lee, Siu Lung Chan, Kwang Ho Kim, Man Lung Mui
  • Shared bit line string architecture
    Patent number: 8879331
    Abstract: Methods for programming and reading memory cells using a shared bit line string architecture are described. In some embodiments, memory cells and select devices may correspond with transistors including a charge storage layer. In some cases, the charge storage layer may be conductive (e.g., a polysilicon layer as used in a floating gate device) or non-conductive (e.g., a silicon nitride layer as used in a SONOS device). In some embodiments, selection of a memory cell in a first string of a pair of strings may include setting an SEO transistor into a conducting state and setting an SGD line controlling drain-side select transistors to a voltage that is greater than a first threshold voltage associated with a first drain-side select transistor of the first string and less than a second threshold voltage associated with a second drain-side select transistor of a second string of the pair of strings.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: November 4, 2014
    Assignee: Sandisk Technologies Inc.
    Inventors: Jongsun Sel, Seungpil Lee, Kwang-Ho Kim, Tuan Pham
  • Semiconductor storage device and method of throttling performance of the same
    Patent number: 8856424
    Abstract: A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device, and a controller configured to receive a write command from a host and program and to write data received from the host to the non-volatile memory device in response to the write command. The controller inserts idle time after receiving the write data from the host and/or after programming the write data to the non-volatile memory device.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: October 7, 2014
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Han Bin Yoon, Yeong-Jae Woo, Dong Gi Lee, Kwang Ho Kim, Hyuck-Sun Kwon
  • SHARED BIT LINE STRING ARCHITECTURE
    Publication number: 20140269100
    Abstract: Methods for programming and reading memory cells using a shared bit line string architecture are described. In some embodiments, memory cells and select devices may correspond with transistors including a charge storage layer. In some cases, the charge storage layer may be conductive (e.g., a polysilicon layer as used in a floating gate device) or non-conductive (e.g., a silicon nitride layer as used in a SONOS device). In some embodiments, selection of a memory cell in a first string of a pair of strings may include setting an SEO transistor into a conducting state and setting an SGD line controlling drain-side select transistors to a voltage that is greater than a first threshold voltage associated with a first drain-side select transistor of the first string and less than a second threshold voltage associated with a second drain-side select transistor of a second string of the pair of strings.
    Type: Application
    Filed: March 12, 2013
    Publication date: September 18, 2014
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Jongsun Sel, Seungpil Lee, Kwang-Ho Kim, Tuan Pham
  • Mobile device and computational system including same
    Patent number: 8838857
    Abstract: A mobile device and a computational system including same are described. The mobile device includes a sensor unit having a motion sensor and/or a touch sensor that provides sensing information. The sensing information is applied to a universal serial bus user interface (USB UI) data generation unit and is changed into USB UI data before being output as USB UI data using a USB communication technique.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: September 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-soo Yang, Kwang-ho Kim, Yong-suk Kim, Taek-kyun Shin