Abstract: In one example, a semiconductor device comprises a main substrate having a top side and a bottom side, a first electronic component on the top side of the main substrate, a second electronic component on the bottom side of the main substrate, a substrate structure on the bottom side of the main substrate adjacent to the second electronic component, and an encapsulant structure comprising an encapsulant top portion on the top side of the main substrate and contacting a side of the first electronic component, and an encapsulant bottom portion on the bottom side of the main substrate and contacting a side of the second electronic component and a side of the substrate structure. Other examples and related methods are also disclosed herein.

Abstract: A vertical memory device includes a substrate, a plurality of gate electrodes vertically stacked over the substrate in a cell array region, and a plurality of multi-layered pad portions formed over the substrate in a contact region. Each multi-layered pad portion of the plurality of multi-layered pad portions extends from an end of a gate electrode of the plurality of gate electrodes. Each multi-layered pad portion of the plurality of multi-layered pad portions includes a lower pad, an upper pad spaced vertically apart from the lower pad, a buffer pad formed between the lower pad and the upper pad, and a pad interconnection portion interconnecting the lower pad and the upper pad.

Abstract: A semiconductor device comprises a substrate having a substrate top side, a substrate lateral side, and a substrate bottom side, an electronic device on the substrate top side, and an encapsulant on the substrate top side and contacting a lateral surface of the electronic device. The substrate comprises a conductive structure and a dielectric structure that extends comprising a protrusion in contact with the encapsulant. The conductive structure comprises a lead comprising a lead flank, the lead flank comprising a cavity and a conductive coating on a surface of the lead in the cavity. The conductive structure comprises a pad exposed at the substrate top side, embedded in the dielectric structure, and adjacent to the protrusion, to electrically couple with the electronic device via a first internal interconnect. Other examples and related methods are also disclosed herein.

Abstract: The present specification provides a film defect detection system. The film defect detection system may comprise an image acquisition unit configured to acquire an image of a film in a manufacturing process of the film; a defect detection unit configured to detect defects in the film by analyzing the acquired image of the film, using a machine learning algorithm learned to detect a defect in advance, when receiving the acquired image of the film; and an information output unit configured to output information on the defects in the film detected by the defect detection unit.

Abstract: A vertical memory device includes a substrate, a plurality of gate electrodes vertically stacked over the substrate in a cell array region, and a plurality of multi-layered pad portions formed over the substrate in a contact region. Each multi-layered pad portion of the plurality of multi-layered pad portions extends from an end of a gate electrode of the plurality of gate electrodes. Each multi-layered pad portion of the plurality of multi-layered pad portions includes a lower pad, an upper pad spaced vertically apart from the lower pad, a buffer pad formed between the lower pad and the upper pad, and a pad interconnection portion interconnecting the lower pad and the upper pad.

Abstract: Provided is an electronic device including a semiconductor memory.

Abstract: A thin semiconductor device with enhanced edge protection, and a method of manufacturing thereof. For example and without limitation, various aspects of this disclosure provide a thin semiconductor device comprising a substrate with an edge-protection region, and a method of manufacturing thereof.

Abstract: Provided is a composition comprising 2,4,6-trihydroxyacetophenone (THA) as an active ingredient, and a method for preventing, alleviating or treating breast cancer using the composition by inhibiting the activity of polo-like kinase 1 (PLK1).

Abstract: A thin semiconductor device with enhanced edge protection, and a method of manufacturing thereof. For example and without limitation, various aspects of this disclosure provide a thin semiconductor device comprising a substrate with an edge-protection region, and a method of manufacturing thereof.

Abstract: Provided is an electronic device including a semiconductor memory.

Abstract: Provided is an electronic device including a semiconductor memory, The semiconductor memory may include: a first channel layer formed over a substrate and extending in a vertical direction; a first stacked structure comprising a plurality of first interlayer dielectric layers and a plurality of first gate electrode layers which are alternately stacked along the first channel layer; a first memory layer interpose d between the first channel layer and the first gate electrode layers; a second channel layer formed over the first channel layer and extending in the vertical, direction; a second stacked structure comprising, a plurality of second interlayer dielectric layers and a plurality of second gate electrode layers which are alternately stacked along the second channel layer; a second memory layer interposed between the second channel layer and the second gate electrode layers; a first channel connection pattern formed between the first channel layer and the second channel layer and coupling the first and th

Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a substrate; and a stepped structure including first interlayer dielectric layers and conductive layers which are alternately stacked over the substrate, wherein ends of the conductive layers are exposed along the profile of the stepped structure, and the stepped structure further includes a barrier layer formed on a sidewall of the conductive layer.

Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a substrate; and a stepped structure including first interlayer dielectric layers and conductive layers which are alternately stacked over the substrate, wherein ends of the conductive layers are exposed along the profile of the stepped structure, and the stepped structure further includes a barrier layer formed on a sidewall of the conductive layer.

Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a substrate; and a stepped structure including first interlayer dielectric layers and conductive layers which are alternately stacked over the substrate, wherein ends of the conductive layers are exposed along the profile of the stepped structure, and the stepped structure further includes a barrier layer formed on a sidewall of the conductive layer.

Abstract: A thin semiconductor device with enhanced edge protection, and a method of manufacturing thereof. For example and without limitation, various aspects of this disclosure provide a thin semiconductor device comprising a substrate with an edge-protection region, and a method of manufacturing thereof.

Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a substrate; and a stepped structure including first interlayer dielectric layers and conductive layers which are alternately stacked over the substrate, wherein ends of the conductive layers are exposed along the profile of the stepped structure, and the stepped structure further includes a barrier layer formed on a sidewall of the conductive layer.

Abstract: A nonvolatile memory device may include a stair-shaped structure including a first interlayer dielectric layer and a memory cell repeatedly stacked. The nonvolatile memory device may include an etch stop layer and a second interlayer dielectric layer formed over the stair-shaped structure. The nonvolatile memory device may include an isolation layer passing through the stair-shaped structure, the etch stop layer, and the second interlayer dielectric layer. The nonvolatile memory device may include protective layer interposed between the isolation layer and the etch stop layer, and the protective layer interposed between the isolation layer and the second interlayer dielectric layer. The nonvolatile memory device may include contact plugs coupled to each memory cell, respectively, by passing through the second interlayer dielectric layer and the etch stop layer.

Abstract: A semiconductor device and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a method of manufacturing a semiconductor package, and a semiconductor package resulting therefrom, that comprises attaching at least one semiconductor die to a metal plate, encapsulating the at least one semiconductor die on the metal plate using an encapsulant, and dicing the metal plate and the encapsulant.

Abstract: Provided is an electronic device including a semiconductor memory, The semiconductor memory may include: a first channel layer formed over a substrate and extending in a vertical direction; a first stacked structure comprising a plurality of first interlayer dielectric layers arid a plurality of first gate electrode layers which are alternately stacked along the first channel layer; a first memory layer interpose d between the first channel layer and the first gate electrode layers; a second channel layer formed over the first channel layer and extending in the vertical, direction; a second stacked structure comprising, a plurality of second interlayer dielectric layers and a plurality of second gate electrode layers which are alternately stacked along the second channel layer; a second memory layer interposed between the second channel layer and the second gate electrode layers; a first channel connection pattern formed between the first channel layer and the second channel layer and coupling the first and t

Abstract: A nonvolatile memory device may include a stair-shaped structure including a first interlayer dielectric layer and a memory cell repeatedly stacked. The nonvolatile memory device may include an etch stop layer and a second interlayer dielectric layer formed over the stair-shaped structure. The nonvolatile memory device may include an isolation layer passing through the stair-shaped structure, the etch stop layer, and the second interlayer dielectric layer. The nonvolatile memory device may include protective layer interposed between the isolation layer and the etch stop layer, and the protective layer interposed between the isolation layer and the second interlayer dielectric layer. The nonvolatile memory device may include contact plugs coupled to each memory cell, respectively, by passing through the second interlayer dielectric layer and the etch stop layer.