Abstract: An image sensor module having a sensor chip closely adhered on a concave surface and a fabrication method thereof are disclosed. The image sensor module includes at least one sensor chip, at least one sensor chip-mounting structure comprising a substrate and a polymer layer formed on the substrate, the polymer layer having an concave surface formed on an upper part thereof by a polymer molding method, so that the sensor chip is bent and bonded on the concave surface, and at least one lens fixed on the at least one sensor chip-mounting structure above the sensor chip.

Abstract: A fabrication method of a wafer level packaging cap for covering a device wafer provided with a device thereon, includes forming an insulating layer on a wafer; removing a predetermined part of the insulating layer and exposing an upper surface of the wafer; forming a cap pad extending from an upper surface and the exposed surface of the wafer; forming a cavity on a lower surface of the wafer corresponding to the cap pad; etching a bottom surface of the cavity and exposing the cap pad which is connected to the wafer through the cavity; and forming metal lines extending from the lower surface of the wafer and the cavity, to electrically connect the cap pad which is exposed through the cavity.

Abstract: A cap for a semiconductor device package, including a body formed at a predetermined thickness with a cavity. The cap further includes a first seed layer formed on an inner circumference of a first via hole formed at a predetermined depth from the cavity formation surface of the body, a second seed layer formed on an inner circumference of a second via hole formed at a predetermined depth from the opposite surface to the cavity formation surface of the body, and plating materials filled in the first via hole and the second via hole.

Abstract: A bulk acoustic resonance and a method for fabricating the bulk acoustic resonator, the bulk acoustic resonator including: a substrate including an upper surface defining a predetermined area including a cavity; a resonance part positioned above the cavity and including a surface comprising a dimple; and an anchor part connecting the resonance part to the substrate. The resonance part includes: a lower electrode including a lower surface including a predetermined dimpled area and an upper surface opposite to the predetermined dimpled area; a piezoelectric layer stacked on the upper surface of the lower electrode; and an upper electrode stacked on the piezoelectric layer. Because direction of the vibration of the resonator is adjustable by adjusting position, area, and the number of the dimples, process freedom can be improved.

Abstract: An image forming element includes a drum body including a plurality of conductive layers and a plurality of insulating layers stacked on one another in an alternate pattern, in which a portion of each of the conductive layers extends towards a cavity defined within the conductive layers to form a plurality of electrodes, and a control unit disposed in the cavity, and including a plurality of electrode pads corresponding to the electrodes to provide an electrical connection to the respective electrodes. Structure and processes to fabricate an image forming element are simplified, and fabricating cost can be reduced.

Abstract: A monolithic duplexer and a fabrication method thereof. The monolithic duplexer includes a device wafer, a plurality of elements distanced from each other on a top portion of a device wafer, first sealing parts formed on the top portion of the device wafer, and a plurality of first ground planes formed between the plurality of elements. A cap wafer is also provided having an etched area for packaging the device wafer, a plurality of protrusion parts, a plurality of ground posts, and cavities. Second sealing parts are formed on a bottom portion of the protrusion parts, and a plurality of second ground planes cover the plurality of ground posts. Via holes vertically penetrate the cap wafer to connect to the plurality of the second ground planes, and ground terminals are formed on top portions of the via holes. The first sealing parts and the first ground planes are attached to the second sealing parts and the second ground planes, respectively.

Abstract: A packaging chip in which a circuit module is packaged and a method of packaging a circuit module are provided. The packaging chip includes a base wafer; a circuit module on the base wafer; a packaging wafer having a cavity and combined with the base wafer so that the circuit module fits inside the cavity; a connecting electrode connecting upper and lower surfaces of the cavity; and a seed layer between the connecting electrode and the packaging wafer. The method includes etching a lower surface of the packaging wafer to form a cavity, stacking a metal layer in an area of the lower surface, combining the base wafer with the packaging wafer, polishing the packaging wafer, forming a viahole through the packaging wafer, stacking a seed layer on the packaging wafer, plating the inside of the viahole, removing the seed layer and forming an electrode.

Abstract: An optical lens is provided. The optical lens provides miniaturization and thin size, and reduces the cost and improves productivity by simplifying the structure and manufacturing process. The optical lens includes a light-transmitting substrate with a lens chamber and a fluidic chamber that are connected with each other. The optical lens also includes a light-transmitting elastic film which seals the lens chamber, a buffer elastic film which seals the fluidic chamber, and an actuator on the buffer elastic film which corresponds to the fluidic chamber, and varies the volume of the fluidic chamber to vary a pressure acting on the light-transmitting elastic film.

Abstract: A multi stack packaging chip and a method of manufacturing the chip are provided. The method includes forming at least one second circuit element on a first wafer; forming a second wafer having a cavity and a one third circuit element formed opposite to the cavity; forming a solder on the second wafer; and combining the second wafer with the first wafer so that the second circuit element and the cavity correspond. The chip includes a flip-chip packaged chip in which a first circuit element is packaged using a first wafer; a second circuit element formed on the first wafer; a second wafer having a cavity and combined with the first wafer so that the cavity and the second circuit element correspond; a third circuit element formed on the second wafer; and a solder formed on the second wafer, the solder electrically coupling the second wafer to a packaging substrate.

Abstract: An image pickup device comprises: a sensor substrate having image sensors arranged in its image pickup region in the form of a matrix; an interlayer insulating film layer formed below a bottom of the sensor substrate, the interlayer insulating film layer including wiring layers formed therein to construct an electric circuit, the wiring layer being electrically connected with the image sensors; a support substrate attached on a bottom of the interlayer insulating film layer, the support substrate having contact electrodes formed in via holes; a lens layer formed over the top surface of the sensor substrate to be opposite to the interlayer insulating film layer; and a light-transmitting member formed over the lens layer.

Abstract: A micro-element package module which can reduce manufacturing costs and can be advantageous for mass production due to simplifying its structure and manufacturing process, and also can facilitate miniaturization and promote thinness, and a method of manufacturing the micro-element package module. The micro-element package module includes: an element substrate having a micro-element on a top surface of the element substrate; a circuit substrate that is provided around the element substrate; and an element housing that is provided above the element substrate and the circuit substrate, and includes a connecting section for electrically connecting the micro-element and the circuit substrate.

Abstract: A micro-element package which can reduce manufacturing costs and can be advantageous for mass production due to simplifying its structure and manufacturing process, and also can facilitate miniaturization and promote thinness, and a method of manufacturing the micro-element package. The micro-element package includes: a substrate having a micro-element on its top surface and a comparatively thin surrounding portion provided around the micro-element; and a circuit board that is electrically connected to the micro-element by utilizing the surrounding portion as a medium.

Abstract: A method of manufacturing a micro-element package which can reduce a manufacturing cost and improve productivity by simplifying its structure and manufacturing process, and also can make contributions to miniaturization and thinness, and the micro-element package are provided. The method of the micro-element package including: providing a substrate having a micro-element on its top surface and a transparent cover having a groove on its bottom surface; attaching the transparent cover on the substrate, wherein the bottom surface of the transparent cover where the groove is formed faces the micro-element; exposing the groove by selectively eliminating the transparent cover; and dicing the substrate along the exposed groove.

Abstract: A fabrication method of a wafer level packaging cap for covering a device wafer provided with a device thereon, includes forming an insulating layer on a wafer; removing a predetermined part of the insulating layer and exposing an upper surface of the wafer; forming a cap pad extending from an upper surface and the exposed surface of the wafer; forming a cavity on a lower surface of the wafer corresponding to the cap pad; etching a bottom surface of the cavity and exposing the cap pad which is connected to the wafer through the cavity; and forming metal lines extending from the lower surface of the wafer and the cavity, to electrically connect the cap pad which is exposed through the cavity.

Abstract: A method and apparatus for vacuum-mounting at least one micro electro mechanical system (MEMS) on a substrate includes a gas injecting section for injecting an inert gas into a vacuum chamber; a substrate aligning section for aligning a semiconductor substrate and a cover, the cover having a cavity formed therein and a getter attached to an interior surface of the cavity; a bonding section for bonding the semiconductor substrate and the cover together; and a controlling section for controlling the substrate aligning section to align the semiconductor and the cover, for controlling the gas injecting section to inject the inert gas into the vacuum chamber, and for controlling the bonding section to bond the semiconductor substrate and the cover together after the inert gas is injected.

Abstract: A monolithic duplexer and a fabrication method thereof. The monolithic duplexer includes a device wafer, a plurality of elements distanced from each other on a top portion of a device wafer, first sealing parts formed on the top portion of the device wafer, and a plurality of first ground planes formed between the plurality of elements. A cap wafer is also provided having an etched area for packaging the device wafer, a plurality of protrusion parts, a plurality of ground posts, and cavities. Second sealing parts are formed on a bottom portion of the protrusion parts, and a plurality of second ground planes cover the plurality of ground posts. Via holes vertically penetrate the cap wafer to connect to the plurality of the second ground planes, and ground terminals are formed on top portions of the via holes. The first sealing parts and the first ground planes are attached to the second sealing parts and the second ground planes, respectively.

Abstract: A packaging chip formed with plural wafers. The packaging chip includes plural wafers stacked in order and plural interconnection electrodes directly connecting the plural wafers from an upper surface of an uppermost wafer of the plural wafers to the other wafers. At least one or more of the plural wafers mounts a predetermined circuit device thereon. Further, at least one or more wafers of the plural wafers have a cavity of a predetermined size. Meanwhile, the packaging chip further includes plural pads independently arranged on the upper surface of the uppermost wafer one another and electrically connected to the plural interconnection electrodes respectively. Accordingly, the present invention can enhance the performance and reliability of a packaging chip and improve fabrication yield.

Abstract: A bulk acoustic resonance and a method for fabricating the bulk acoustic resonator, the bulk acoustic resonator including: a substrate including an upper surface defining a predetermined area including a cavity; a resonance part positioned above the cavity and including a surface comprising a dimple; and an anchor part connecting the resonance part to the substrate. The resonance part includes: a lower electrode including a lower surface including a predetermined dimpled area and an upper surface opposite to the predetermined dimpled area; a piezoelectric layer stacked on the upper surface of the lower electrode; and an upper electrode stacked on the piezoelectric layer. Because direction of the vibration of the resonator is adjustable by adjusting position, area, and the number of the dimples, process freedom can be improved.

Abstract: A cap for a semiconductor device package, including a body formed at a predetermined thickness with a cavity. The cap further includes a first seed layer formed on an inner circumference of a first via hole formed at a predetermined depth from the cavity formation surface of the body, a second seed layer formed on an inner circumference of a second via hole formed at a predetermined depth from the opposite surface to the cavity formation surface of the body, and plating materials filled in the first via hole and the second via hole.

Abstract: A packaging chip in which a circuit module is packaged and a method of packaging a circuit module are provided. The packaging chip includes a base wafer; a circuit module on the base wafer; a packaging wafer having a cavity and combined with the base wafer so that the circuit module fits inside the cavity; a connecting electrode connecting upper and lower surfaces of the cavity; and a seed layer between the connecting electrode and the packaging wafer. The method includes etching a lower surface of the packaging wafer to form a cavity, stacking a metal layer in an area of the lower surface, combining the base wafer with the packaging wafer, polishing the packaging wafer, forming a viahole through the packaging wafer, stacking a seed layer on the packaging wafer, plating the inside of the viahole, removing the seed layer and forming an electrode.