Patents by Inventor Kyu-dong Jung

Kyu-dong Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060255443
    Abstract: A multi stack packaging chip and a method of manufacturing the chip are provided. The method includes forming at least one second circuit element on a first wafer; forming a second wafer having a cavity and a one third circuit element formed opposite to the cavity; forming a solder on the second wafer; and combining the second wafer with the first wafer so that the second circuit element and the cavity correspond. The chip includes a flip-chip packaged chip in which a first circuit element is packaged using a first wafer; a second circuit element formed on the first wafer; a second wafer having a cavity and combined with the first wafer so that the cavity and the second circuit element correspond; a third circuit element formed on the second wafer; and a solder formed on the second wafer, the solder electrically coupling the second wafer to a packaging substrate.
    Type: Application
    Filed: March 29, 2006
    Publication date: November 16, 2006
    Inventors: Jun-sik Hwang, Woon-bae Kim, Chang-youl Moon, Moon-chul Lee, Kyu-dong Jung
  • Publication number: 20060175707
    Abstract: A wafer level packaging cap and method thereof for a wafer level packaging are provided. The wafer level packaging cap covering a device wafer with a device thereon, includes a cap wafer having on a bottom surface a cavity providing a space for receiving the device, and integrally combined with the device wafer, a plurality of metal lines formed on the bottom surface of the cap wafer to correspond to a plurality of device pads formed on the device wafer to be electrically connected to the device, a plurality of buffer portions connected to the plurality of metal lines and comprising a buffer wafer with a plurality of grooves and a metal filled in the plurality of grooves, a plurality of connection rods electrically connected to the plurality of buffer portions and penetrating the cap wafer from a top portion of the buffer portion, and a plurality of cap pads formed on a top surface of the cap wafer and electrically connected to a plurality of connection rods.
    Type: Application
    Filed: January 26, 2006
    Publication date: August 10, 2006
    Inventors: Moon-chul Lee, Woon-bae Kim, Kae-dong Back, Qian Wang, Jun-sik Hwang, Kyu-dong Jung
  • Patent number: 7084073
    Abstract: A method of forming a via hole through a glass wafer includes depositing a material layer on an outer surface of the glass wafer, the material layer having a selection ratio higher than that of the glass wafer, forming a via-patterned portion on one side of the material layer, performing a first etching in which the via-patterned portion is etched to form a preliminary via hole, eliminating any remaining patterning material used in the formation of the via-patterned portion, performing a second etching in which the preliminary via hole is etched to form a via hole having a smooth surface and extending through the glass wafer, and eliminating the material layer. The method according to the present invention is able to form a via hole through a glass wafer without allowing formation of an undercut or minute cracks, thereby increasing the yield and reliability of MEMS elements.
    Type: Grant
    Filed: October 9, 2003
    Date of Patent: August 1, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moon-chul Lee, Hyung Choi, Kyu-dong Jung, Mi Jang, Seog-woo Hong, Seok-whan Chung, Chan-bong Jun, Seok-jin Kang
  • Patent number: 6952965
    Abstract: A vertical MEMS gyroscope by horizontal driving includes a substrate, a support layer fixed on an upper surface of an area of the substrate, a driving structure floating above the substrate and having a portion fixed to an upper surface of the support layer and another portion in parallel with the fixed portion, the driving structure having a predetermined area capable of vibrating in a predetermined direction parallel to the substrate, a detecting structure fixed to the driving structure on a same plane as the driving structure, and having a predetermined area capable of vibrating in a vertical direction with respect to the substrate, a cap wafer bonded with the substrate positioned above the driving structure and the detecting structure, and a fixed vertical displacement detection electrode formed at a predetermined location of an underside of the cap wafer, for detecting displacement of the detecting structure in the vertical direction.
    Type: Grant
    Filed: December 24, 2003
    Date of Patent: October 11, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-jin Kang, Seok-whan Chung, Moon-chul Lee, Kyu-dong Jung, Seog-soo Hong
  • Patent number: 6835594
    Abstract: A metal wiring method for an undercut in a MEMS packaging process includes disposing a MEMS element on a silicon substrate, welding a glass wafer to an upper portion of the silicon substrate having the MEMS element disposed thereon, the glass wafer having a hole formed therein for connecting a metal wiring, depositing a thin metal film for the metal wiring in the hole, and ion-mealing the deposited thin metal film. By the ion-mealing, the method is capable of connecting a metal wiring to a via hole having an undercut.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: December 28, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ci-moo Shong, Seok-jin Kang, Seok-whan Chung, Moon-chul Lee, Kyu-dong Jung, Jong-seok Kim, Chan-bong Jun, Seog-woo Hong, Jung-ho Kang
  • Publication number: 20040226369
    Abstract: A vertical MEMS gyroscope by horizontal driving includes a substrate, a support layer fixed on an upper surface of an area of the substrate, a driving structure floating above the substrate and having a portion fixed to the upper surface of the support layer and another portion in parallel with the fixed portion, the driving structure having a predetermined area capable of vibrating in a predetermined direction parallel to the substrate, a detection structure fixed to the driving structure on a same plane as the driving structure, and having a predetermined area capable of vibrating in a vertical direction with respect to the substrate, a cap wafer bonded with the substrate positioned above the driving structure and the detection structure, and a fixed vertical displacement detection electrode formed at a predetermined location of an underside of the cap wafer, for detecting displacement of the detection structure in the vertical direction.
    Type: Application
    Filed: December 24, 2003
    Publication date: November 18, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Seok-jin Kang, Seok-whan Chung, Moon-chul Lee, Kyu-dong Jung, Seog-soo Hong
  • Publication number: 20040203186
    Abstract: A metal wiring method for an undercut in a MEMS packaging process includes disposing a MEMS element on a silicon substrate, welding a glass wafer to an upper portion of the silicon substrate having the MEMS element disposed thereon, the glass wafer having a hole formed therein for connecting a metal wiring, depositing a thin metal film for the metal wiring in the hole, and ion-mealing the deposited thin metal film. By the ion-mealing, the method is capable of connecting a metal wiring to a via hole having an undercut.
    Type: Application
    Filed: October 17, 2003
    Publication date: October 14, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ci-moo Shong, Seok-jin Kang, Seok-whan Chung, Moon-chul Lee, Kyu-dong Jung, Jong-seok Kim, Chan-bong Jun, Seog-woo Hong, Jung-ho Kang
  • Publication number: 20040115856
    Abstract: A method and apparatus for vacuum-mounting at least one micro electro mechanical system (MEMS) on a substrate includes a gas injecting section for injecting an inert gas into a vacuum chamber; a substrate aligning section for aligning a semiconductor substrate and a cover, the cover having a cavity formed therein and a getter attached to an interior surface of the cavity; a bonding section for bonding the semiconductor substrate and the cover together; and a controlling section for controlling the substrate aligning section to align the semiconductor and the cover, for controlling the gas injecting section to inject the inert gas into the vacuum chamber, and for controlling the bonding section to bond the semiconductor substrate and the cover together after the inert gas is injected.
    Type: Application
    Filed: November 6, 2003
    Publication date: June 17, 2004
    Inventors: Kyu-Dong Jung, Chan-Bong Jun, Hyung Choi, Seok-Jin Kang, Seog-Woo Hong, Seok-Whan Chung, Moon-Chul Lee, Eun-Sung Lee
  • Patent number: 6739189
    Abstract: Provided are a structure for detecting a vertical displacement and its manufacturing method. The structure for detecting a vertical displacement includes a body, an inertial mass floated over the body, a plurality of support beams extending from the inertial mass so as to suspend the inertial mass over the body, movable electrodes integrally formed with the inertial mass, and fixed electrodes floated over the body, each being positioned between the neighboring movable electrodes, wherein a vertical length of the movable electrode is different from a vertical length of the fixed electrode. Therefore, the structure and the electrodes can be simultaneously manufactured, thereby making the fabrication process simple. Also, it is possible to manufacture a three-axis accelerometer and a three-axis gyroscope on a single wafer by the same process, to be integrated as a six-axis inertial sensor.
    Type: Grant
    Filed: April 15, 2002
    Date of Patent: May 25, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byeung-leul Lee, Kyu-dong Jung, Sang-woo Lee, Yong-chul Cho
  • Publication number: 20040092105
    Abstract: A method of forming a via hole through a glass wafer includes depositing a material layer on an outer surface of the glass wafer, the material layer having a selection ratio higher than that of the glass wafer, forming a via-patterned portion on one side of the material layer, performing a first etching in which the via-patterned portion is etched to form a preliminary via hole, eliminating any remaining patterning material used in the formation of the via-patterned portion, performing a second etching in which the preliminary via hole is etched to form a via hole having a smooth surface and extending through the glass wafer, and eliminating the material layer. The method according to the present invention is able to form a via hole through a glass wafer without allowing formation of an undercut or minute cracks, thereby increasing the yield and reliability of MEMS elements.
    Type: Application
    Filed: October 9, 2003
    Publication date: May 13, 2004
    Inventors: Moon-chul Lee, Hyung choi, Kyu-dong Jung, Mi Jang, Seog-woo Hong, Seok-whan Chung, Chan-bong Jun, Seok-jin Kang
  • Patent number: 6719918
    Abstract: A method of reducing notching during reactive ion etching (RIE) is provided. The method is useful when RIE is performed to pass through a silicon layer on a multi-layered structure on which the silicon layer, an insulating layer and a silicon substrate are sequentially deposited. The method includes the steps of: forming an insulating layer on a silicon substrate; forming trenches on the insulating layer to expose the silicon substrate; forming a silicon layer on the insulating layer to fill the trenches; and patterning the silicon layer to form first etch regions, which pass through the silicon layer, to include the trenches. According to the method, it is possible to remarkably reduce notching without depositing a metal layer, when a multi-layered structure including a silicon layer which is etched to be passed through during RIE is fabricated.
    Type: Grant
    Filed: December 26, 2001
    Date of Patent: April 13, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byeung-leul Lee, Taek-ryong Chung, Joon-hyock Choi, Won-youl Choi, Kyu-dong Jung, Sang-woo Lee
  • Publication number: 20020158293
    Abstract: Provided are a structure for detecting a vertical displacement and its manufacturing method. The structure for detecting a vertical displacement includes a body, an inertial mass floated over the body, a plurality of support beams extending from the inertial mass so as to suspend the inertial mass over the body, movable electrodes integrally formed with the inertial mass, and fixed electrodes floated over the body, each being positioned between the neighboring movable electrodes, wherein a vertical length of the movable electrode is different from a vertical length of the fixed electrode. Therefore, the structure and the electrodes can be simultaneously manufactured, thereby making the fabrication process simple. Also, it is possible to manufacture a three-axis accelerometer and a three-axis gyroscope on a single wafer by the same process, to be integrated as a six-axis inertial sensor.
    Type: Application
    Filed: April 15, 2002
    Publication date: October 31, 2002
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Byeung-leul Lee, Kyu-dong Jung, Sang-woo Lee, Yong-chul Cho
  • Publication number: 20020125211
    Abstract: A method of reducing notching during reactive ion etching (RIE) is provided. The method is useful when RIE is performed to pass through a silicon layer on a multi-layered structure on which the silicon layer, an insulating layer and a silicon substrate are sequentially deposited. The method includes the steps of: forming an insulating layer on a silicon substrate; forming trenches on the insulating layer to expose the silicon substrate; forming a silicon layer on the insulating layer to fill the trenches; and patterning the silicon layer to form first etch regions, which pass through the silicon layer, to include the trenches. According to the method, it is possible to remarkably reduce notching without depositing a metal layer, when a multi-layered structure including a silicon layer which is etched to be passed through during RIE is fabricated.
    Type: Application
    Filed: December 26, 2001
    Publication date: September 12, 2002
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Byeung-Leul Lee, Taek-Ryong Chung, Joon-Hyock Choi, Won-Youl Chol, Kyu-Dong Jung, Sang-Woo Lee