Abstract: Methods of forming sensor integrated package devices and structures formed thereby are described. An embodiment includes providing a substrate core, wherein a first conductive trace structure and a second conductive trace structure are disposed on the substrate core, forming a cavity between the first conductive trace structure and the second conductive trace structure, and placing a magnet on a resist material disposed on a portion of each of the first and second conductive trace structures, wherein the resist material does not extend over the cavity.

Abstract: A pressure sensor is integrated into an integrated circuit fabrication and packaging flow. In one example, a releasable layer is formed over a removable core. A first dielectric layer is formed. A metal layer is patterned to form conductive metal paths and to form a diaphragm with the metal. A second dielectric layer is formed over the metal layer and the diaphragm. A second metal layer is formed to connect with formed vias and to form a metal mesh layer over the diaphragm. The first dielectric layer is etched under the diaphragm to form a cavity and the cavity is covered to form a chamber adjoining the diaphragm.

Abstract: Reliable microstrip routing arrangements for electronics components are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a semiconductor package substrate by a plurality of conductive contacts. A plurality of discrete metal planes is disposed at the uppermost metallization layer of the semiconductor package substrate, each metal plane located, from a plan view perspective, at a corner of a perimeter of the semiconductor die. Microstrip routing is disposed at the uppermost metallization layer of the semiconductor package substrate, from the plan view perspective, outside of the perimeter of the semiconductor die.

Abstract: Methods of forming sensor integrated package devices and structures formed thereby are described. An embodiment includes providing a substrate core, wherein a first conductive trace structure and a second conductive trace structure are disposed on the substrate core, forming a cavity between the first conductive trace structure and the second conductive trace structure, and placing a magnet on a resist material disposed on a portion of each of the first and second conductive trace structures, wherein the resist material does not extend over the cavity.

Abstract: Reliable microstrip routing arrangements for electronics components are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a semiconductor package substrate by a plurality of conductive contacts. A plurality of discrete metal planes is disposed at the uppermost metallization layer of the semiconductor package substrate, each metal plane located, from a plan view perspective, at a corner of a perimeter of the semiconductor die. Microstrip routing is disposed at the uppermost metallization layer of the semiconductor package substrate, from the plan view perspective, outside of the perimeter of the semiconductor die.

Abstract: A pressure sensor is integrated into an integrated circuit fabrication and packaging flow. In one example, a releasable layer is formed over a removable core. A first dielectric layer is formed. A metal layer is patterned to form conductive metal paths and to form a diaphragm with the metal. A second dielectric layer is formed over the metal layer and the diaphragm. A second metal layer is formed to connect with formed vias and to form a metal mesh layer over the diaphragm. The first dielectric layer is etched under the diaphragm to form a cavity and the cavity is covered to form a chamber adjoining the diaphragm.

Abstract: Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.

Abstract: The integration of pressure or inertial sensors into an integrated circuit fabrication and packaging flow is described. In one example, a diaphragm is formed by depositing a metal over a first dielectric layer. A second dielectric layer is formed over the diaphragm. A metal mesh layer is formed over the second dielectric. The first dielectric layer is etched under the diaphragm to form a cavity. The cavity is lined with a sealing layer. The cavity is covered to form a chamber adjoining the diaphragm, and the cover is sealed against the cavity.

Abstract: This disclosure relates generally to an electronic assembly and methods that include a dielectric material forming a cavity, a magnet positioned to induce a magnetic field within the cavity, a conductive trace positioned, at least in part, within the cavity, and a frequency detection circuit configured to detect the frequency of the maximal electromotive force as induced and produce an output proportional to a temperature of the conductive trace.

Abstract: Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.

Abstract: Reliable microstrip routing arrangements for electronics components are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a semiconductor package substrate by a plurality of conductive contacts. A plurality of discrete metal planes is disposed at the uppermost metallization layer of the semiconductor package substrate, each metal plane located, from a plan view perspective, at a corner of a perimeter of the semiconductor die. Microstrip routing is disposed at the uppermost metallization layer of the semiconductor package substrate, from the plan view perspective, outside of the perimeter of the semiconductor die.

Abstract: Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.

Abstract: The integration of pressure or inertial sensors into an integrated circuit fabrication and packaging flow is described. In one example, a diaphragm is formed by depositing a metal over a first dielectric layer. A second dielectric layer is formed over the diaphragm. A metal mesh layer is formed over the second dielectric. The first dielectric layer is etched under the diaphragm to form a cavity. The cavity is lined with a sealing layer. The cavity is covered to form a chamber adjoining the diaphragm, and the cover is sealed against the cavity.

Abstract: Magnet placement is described for integrated circuit packages. In one example, a terminal is applied to a magnet. The magnet is then placed on a top layer of a substrate with solder between the terminal and the top layer, and the solder is reflowed to attach the magnet to the substrate.

Abstract: A semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a semiconductor package substrate by a plurality of conductive contacts. A plurality of discrete metal planes is disposed at the uppermost metallization layer of the semiconductor package substrate, each metal plane located, from a plan view perspective, at a corner of a perimeter of the semiconductor die. Microstrip routing is disposed at the uppermost metallization layer of the semiconductor package substrate, from the plan view perspective, outside of the perimeter of the semiconductor die.

Abstract: A lead-free solder alloy capable of forming solder joints in which electromigration and an increase in resistance during electric conduction at a high current density are suppressed has an alloy composition consisting essentially of 1.0-13.0 mass % of In, 0.1-4.0 mass % of Ag, 0.3-1.0 mass % of Cu, a remainder of Sn. The solder alloy has excellent tensile properties even at a high temperature exceeding 100° C. and can be used not only for CPUs but also for power semiconductors.

Abstract: A lead-free solder alloy consisting essentially of, in mass percent, Bi: 31-59%, Sb: 0.15-0.75%, at least one element selected from Cu: 0.3-1.0% and P: 0.002-0.055%, and a balance of Sn has a low melting point for suppressing warping of a thin substrate during soldering. It can form solder joints with high reliability even when used for soldering to electrodes having a Ni coating which contains P, since the growth of a P-rich layer is suppressed so that the shear strength of the joints is improved and the alloy has a high ductility and a high tensile strength.

Abstract: Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.

Abstract: Reliable microstrip routing arrangements for electronics components are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a semiconductor package substrate by a plurality of conductive contacts. A plurality of discrete metal planes is disposed at the uppermost metallization layer of the semiconductor package substrate, each metal plane located, from a plan view perspective, at a corner of a perimeter of the semiconductor die. Microstrip routing is disposed at the uppermost metallization layer of the semiconductor package substrate, from the plan view perspective, outside of the perimeter of the semiconductor die.

Abstract: Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.