Patents by Inventor Kyu Oh Lee

Kyu Oh Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10373900
    Abstract: Techniques and mechanisms for providing effective connectivity with surface level microbumps on an integrated circuit package substrate. In an embodiment, different metals are variously electroplated to form a microbump which extends through a surface-level dielectric of a substrate to a seed layer including copper. The microbump includes a combination of tin and zinc that mitigates precipitation of residual copper by promoting the formation of miconstituents in the microbump. In another embodiment, the microbump has a mass fraction of zinc, or a mass fraction of tin, that is different in various regions along a height of the microbump.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: August 6, 2019
    Assignee: Intel Corporation
    Inventors: Sri Chaitra J. Chavali, Amanda E. Schuckman, Kyu Oh Lee
  • Publication number: 20190221345
    Abstract: A substrate for an integrated circuit package, the substrate comprising a dielectric, at least one conductor plane within the dielectric, and a planar magnetic structure comprising an organic magnetic laminate embedded within the dielectric, wherein the planar magnetic structure is integrated within the at least one conductor plane.
    Type: Application
    Filed: January 12, 2018
    Publication date: July 18, 2019
    Applicant: Intel Corporation
    Inventors: Sai Vadlamani, Prithwish Chatterjee, Rahul Jain, Kyu Oh Lee, Sheng C. Li, Andrew J. Brown, Lauren A. Link
  • Publication number: 20190206822
    Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a resist layer disposed on a conductive layer. The semiconductor package also has a bump disposed on the conductive layer. The bump has a top surface and one or more sidewalls. The semiconductor package further includes a surface finish disposed on the top surface and the one or more sidewalls of the bump. The semiconductor package may have the surface finish surround the top surface and sidewalls of the bumps to protect the bumps from Galvanic corrosion. The surface finish may include a nickel-palladium-gold (NiPdAu) surface finish. The semiconductor package may also have a seed disposed on a top surface of the resist layer, and a dielectric disposed on the seed. The dielectric may surround the sidewalls of the bump. The semiconductor package may include the seed to be an electroless copper seed.
    Type: Application
    Filed: December 30, 2017
    Publication date: July 4, 2019
    Inventors: Ji Yong PARK, Kyu Oh LEE, Cheng XU, Seo Young KIM
  • Publication number: 20190198436
    Abstract: Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material.
    Type: Application
    Filed: December 27, 2017
    Publication date: June 27, 2019
    Applicant: Intel Corporation
    Inventors: Sai Vadlamani, Prithwish Chatterjee, Robert A. May, Rahul S. Jain, Lauren A. Link, Andrew J. Brown, Kyu Oh Lee, Sheng C. Li
  • Publication number: 20190189582
    Abstract: Embodiments are generally directed to indium solder metallurgy to control electro-migration. An embodiment of an electronic device includes a die; and a package substrate, wherein the die is bonded to the package substrate by an interconnection. The interconnection includes multiple interconnects, and wherein the interconnection includes a solder. The solder for the interconnection includes a combination of tin (Sn), copper (Cu), and indium (In).
    Type: Application
    Filed: October 1, 2016
    Publication date: June 20, 2019
    Inventors: Kyu Oh LEE, Yi LI, Yueli LIU
  • Patent number: 10297563
    Abstract: Techniques and mechanisms for providing effective connectivity with surface level microbumps on an integrated circuit package substrate. In an embodiment, different metals are variously electroplated to form a microbump which extends through a surface-level dielectric of a substrate to a seed layer including copper. The microbump includes nickel and tin, wherein the nickel aids in mitigating an absorption of seed layer copper. In another embodiment, the microbump has a mass fraction of tin, or a mass fraction of nickel, that is different in various regions along a height of the microbump.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Rahul Jain, Kyu Oh Lee, Amanda E. Schuckman, Steve S. Cho
  • Publication number: 20190081002
    Abstract: Semiconductor packages with embedded bridge interconnects, and related assemblies and methods, are disclosed herein. In some embodiments, a semiconductor package may have a first side and a second side, and may include a bridge interconnect, embedded in a build-up material, having a first side with a plurality of conductive pads. The semiconductor package may also include a via having a first end that is narrower than a second end. The bridge interconnect and via may be arranged so that the first side of the semiconductor package is closer to the first side of the bridge interconnect than to the second side of the bridge interconnect, and so that the first side of the semiconductor package is closer to the first end of the via than to the second end of the via. Other embodiments may be disclosed and/or claimed.
    Type: Application
    Filed: November 8, 2018
    Publication date: March 14, 2019
    Inventor: Kyu-Oh LEE
  • Publication number: 20190076966
    Abstract: A lead-free solder alloy capable of forming solder joints in which electromigration and an increase in resistance during electric conduction at a high current density are suppressed has an alloy composition consisting essentially of 1.0-13.0 mass % of In, 0.1-4.0 mass % of Ag, 0.3-1.0 mass % of Cu, a remainder of Sn. The solder alloy has excellent tensile properties even at a high temperature exceeding 100° C. and can be used not only for CPUs but also for power semiconductors.
    Type: Application
    Filed: August 13, 2018
    Publication date: March 14, 2019
    Inventors: Tsukasa Ohnishi, Shunsaku Yoshikawa, Ken Tachibana, Yoshie Yamanaka, Hikaru Nomura, Kyu-oh Lee
  • Patent number: 10157847
    Abstract: Semiconductor packages with embedded bridge interconnects, and related assemblies and methods, are disclosed herein. In some embodiments, a semiconductor package may have a first side and a second side, and may include a bridge interconnect, embedded in a build-up material, having a first side with a plurality of conductive pads. The semiconductor package may also include a via having a first end that is narrower than a second end. The bridge interconnect and via may be arranged so that the first side of the semiconductor package is closer to the first side of the bridge interconnect than to the second side of the bridge interconnect, and so that the first side of the semiconductor package is closer to the first end of the via than to the second end of the via. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: December 18, 2018
    Assignee: Intel Corporation
    Inventor: Kyu-Oh Lee
  • Patent number: 10121752
    Abstract: A surface finish may be formed in a microelectronic structure, wherein the surface finish may include a multilayer interlayer structure. Thus, needed characteristics, such as compliance and electro-migration resistance, of the interlayer structure may be satisfied by different material layers, rather attempting to achieve these characteristics with a single layer. In one embodiment, the multilayer interlayer structure may comprises a two-layer structure, wherein a first layer is formed proximate a solder interconnect and comprises a material which forms a ductile joint with the solder interconnect, and a second layer comprising a material having strong electro-migration resistance formed between the first layer and an interconnection pad. In a further embodiment, third layer may be formed adjacent the interconnection pad comprising a material which forms a ductile joint with the interconnection pad.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: November 6, 2018
    Assignee: Intel Corporation
    Inventors: Srinivas V. Pietambaram, Kyu Oh Lee
  • Publication number: 20180281374
    Abstract: A method for forming a substrate structure for an electrical component includes placing an electrically insulating laminate on a substrate and applying hot pressure to the electrically insulating laminate by a heatable plate. An average temperature of a surface temperature distribution within a center area of the heatable plate is higher than 80° C. during applying the hot pressure. Further, an edge area of the heatable plate laterally surrounds the center area and a temperature of the heatable plate within the edge area decreases from the center area towards an edge of the heatable plate during applying the hot pressure. A temperature at a location located vertically above an edge of the substrate during applying the hot pressure is at least 5° C. lower than the average temperature of the surface temperature distribution within the center area.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Inventors: Ji Yong Park, Sri Chaitra J. Chavali, Siddharth K. Alur, Kyu Oh Lee
  • Publication number: 20180286812
    Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Inventors: Rahul Jain, Ji Yong Park, Kyu Oh Lee
  • Patent number: 10076808
    Abstract: A lead-free solder alloy capable of forming solder joints in which electromigration and an increase in resistance during electric conduction at a high current density are suppressed has an alloy composition consisting essentially of 1.0-13.0 mass % of In, 0.1-4.0 mass % of Ag, 0.3-1.0 mass % of Cu, a remainder of Sn. The solder alloy has excellent tensile properties even at a high temperature exceeding 100° C. and can be used not only for CPUs but also for power semiconductors.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: September 18, 2018
    Assignee: Senju Metal Industry Co., Ltd.
    Inventors: Tsukasa Ohnishi, Shunsaku Yoshikawa, Ken Tachibana, Yoshie Yamanaka, Hikaru Nomura, Kyu-oh Lee
  • Publication number: 20180240788
    Abstract: Discussed generally herein are methods and devices for multichip packages that include an inorganic interposer. A device can include a substrate including low density interconnect circuitry therein, an inorganic interposer on the substrate, the inorganic interposer including high density interconnect circuitry electrically connected to the low density interconnect circuitry, the inorganic interposer including inorganic materials, and two or more chips electrically connected to the inorganic interposer, the two or more chips electrically connected to each other through the high density interconnect circuitry.
    Type: Application
    Filed: August 31, 2015
    Publication date: August 23, 2018
    Applicant: Intel Corporation
    Inventors: Daniel Sobieski, Kristof Darmawikarta, Sri Ranga Sai Boyapati, Merve Celikkol, Kyu Oh Lee, Kemal Aygun, Zhiguo Qian
  • Publication number: 20180226381
    Abstract: Disclosed herein are integrated circuit (IC) structures having recessed conductive contacts for package on package (PoP). For example, an IC structure may include: an IC package having a first resist surface; a recess disposed in the first resist surface, wherein a bottom of the recess includes a second resist surface; a first plurality of conductive contacts located at the first resist surface; and a second plurality of conductive contacts located at the second resist surface. Other embodiments may be disclosed and/or claimed.
    Type: Application
    Filed: January 5, 2018
    Publication date: August 9, 2018
    Inventors: KYU-OH LEE, ISLAM A. SALAMA, RAM S. VISWANATH, ROBERT L. SANKMAN, BABAK SABI, SRI CHAITRA JYOTSNA CHAVALI
  • Patent number: 10026691
    Abstract: Package substrates including conductive interconnects having noncircular cross-sections, and integrated circuit packages incorporating such package substrates, are described. In an example, a conductive pillar having a noncircular pillar cross-section is electrically connected to an escape line routing layer. The escape line routing layer may include several series of conductive pads having noncircular pad cross-sections. Accordingly, conductive traces, e.g., strip line escapes and microstrip escapes, may be routed between the series of conductive pads in a single escape line routing layer.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: July 17, 2018
    Assignee: Intel Corporation
    Inventors: Kristof Kuwawi Darmawikarta, Kyu Oh Lee, Daniel Nicholas Sobieski
  • Patent number: 9947631
    Abstract: A surface finish may be formed in a microelectronic structure, wherein the surface finish may include an interlayer comprising a refractory metal, phosphorus, and nickel, with the refractory metal having a content of between about 2 and 12% by weight and the phosphorus having a content of between about 2 and 12% by weight with the remainder being nickel. In one embodiment, the refractory metal of the interlayer may consist of one of tungsten, molybdenum, and ruthenium. In another embodiment, the interlayer may comprise the refractory metal being tungsten having a content of between about 5 and 6% by weight and phosphorus having a content of between about 5 and 6% by weight with the remainder being nickel.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: April 17, 2018
    Assignee: Intel Corporation
    Inventors: Srinivas V. Pietambaram, Kyu-Oh Lee
  • Publication number: 20180076161
    Abstract: Techniques and mechanisms for providing effective connectivity with surface level microbumps on an integrated circuit package substrate. In an embodiment, different metals are variously electroplated to form a microbump which extends through a surface-level dielectric of a substrate to a seed layer including copper. The microbump includes nickel and tin, wherein the nickel aids in mitigating an absorption of seed layer copper. In another embodiment, the microbump has a mass fraction of tin, or a mass fraction of nickel, that is different in various regions along a height of the microbump.
    Type: Application
    Filed: September 15, 2016
    Publication date: March 15, 2018
    Inventors: Rahul Jain, Kyu Oh Lee, Amanda E. Schuckman, Steve S. Cho
  • Publication number: 20180076119
    Abstract: Techniques and mechanisms for providing effective connectivity with surface level microbumps on an integrated circuit package substrate. In an embodiment, different metals are variously electroplated to form a microbump which extends through a surface-level dielectric of a substrate to a seed layer including copper. The microbump includes a combination of tin and zinc that mitigates precipitation of residual copper by promoting the formation of miconstituents in the microbump. In another embodiment, the microbump has a mass fraction of zinc, or a mass fraction of tin, that is different in various regions along a height of the microbump.
    Type: Application
    Filed: November 7, 2017
    Publication date: March 15, 2018
    Inventors: Sri Chaitra J. Chavali, Amanda E. Schuckman, Kyu Oh Lee
  • Patent number: 9917044
    Abstract: Some embodiments of the present disclosure describe a multi-layer package with a bi-layered dielectric structure and associated techniques and configurations. In one embodiment, an integrated circuit (IC) package assembly includes a dielectric structure coupled with a metal layer, with the dielectric structure including a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has a thickness less than a thickness of the second dielectric layer and a dielectric loss tangent greater than a dielectric loss tangent of the second layer. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: March 13, 2018
    Assignee: INTEL CORPORATION
    Inventors: Zheng Zhou, Mihir K. Roy, Chong Zhang, Kyu-Oh Lee, Amanda E. Schuckman