Abstract: An image sensor and a method for fabricating the same are provided, in which the image sensor includes a substrate including a first sensing region having a photoelectric device therein, a boundary isolation film partitioning the first sensing region, an inner reflection pattern film within the substrate in the sensing region, an infrared filter on the substrate, and a micro lens on the infrared filter.

Abstract: A semiconductor device includes a light-receiving element which outputs electric charges in response to incident light, and a drive transistor which is gated by an output of the light-receiving element to generate a source-drain current in proportion to the incident light, wherein the drive transistor include a first gate electrode, a first channel region which is disposed under the first gate electrode, first source-drain regions which are disposed at respective ends of the first channel region and that have a first conductivity type, and a first channel stop region which is disposed on a side of the first channel region, and that separates the light-receiving element and the first channel region, the first channel stop region having a second conductivity type that is different from the first conductivity type.

Abstract: An image sensor according to some example embodiments includes a pixel array unit including a plurality of transmission signal lines and a plurality of output signal lines, and a plurality of pixels connected to the plurality of transmission signal lines and the plurality of output signal lines. Each of the plurality of pixels includes a plurality of photoelectric conversion elements, which are configured to detect and photoelectrically convert incident light. The plurality of pixels include at least one autofocusing pixel and at least one normal pixel.

Abstract: An image sensor includes a photoelectric conversion unit configured to receive light to generate an electric charge and provide the electric charge to a first node, a transfer transistor configured to provide a voltage level of the first node to a floating diffusion node in response to a first signal, a booster configured to increase a voltage level of the floating diffusion node in response to a second signal, a source follower transistor configured to provide the voltage level of the floating diffusion node to a second node, and a selection transistor configured to provide a voltage level of the second node to a pixel output terminal in response to a third signal. After the selection transistor is turned on, the booster is enabled, and before the transfer transistor is turned on, the booster is disabled.

Abstract: A printed circuit board and a method of manufacturing the same are provided. The printed circuit board includes an inner layer including at least one insulating layer and wiring parts, and outer layers disposed on opposing sides of the inner layer, the outer layers including reinforcing layers and wiring parts, the reinforcing layers having a greater degree of rigidity than the insulating layer.

Abstract: Disclosed is an apparatus for managing a risk of a malware behavior in a mobile operating system, which includes: a deducing unit configured to deduce characteristics of a malware from results of a static analysis on mobile malware data and a dynamic analysis thereon under a virtual environment by using a blacklist including an indicator of compromise (IOC) utilized in an existing mobile malware.

Abstract: A semiconductor package includes: a connection member having a first surface and a second surface opposing each other in a stacking direction of the semiconductor package and including an insulating member and a redistribution layer formed on the insulating member and having a redistribution via; a semiconductor chip disposed on the first surface of the connection member and having connection pads connected to the redistribution layer; an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip; a passivation layer disposed on the second surface of the connection member; UBM pads disposed on the passivation layer and overlapping the redistribution vias in the stacking direction; and UBM vias connecting the UBM pads to the redistribution layer through the passivation layer, not overlapping the redistribution vias with respect to the stacking direction, and having a non-circular cross section.

Abstract: A fan-out semiconductor package includes a wiring portion, semiconductor chips, a dummy chip, and an encapsulant. The wiring portion includes an insulating layer, conductive patterns formed on the insulating layer, and conductive vias penetrating through the insulating layer and connected to the conductive patterns. The semiconductor chips are disposed on one region of the wiring portion, and the dummy chip is disposed on another region thereof and has a thickness smaller than those of the semiconductor chips. The encapsulant encapsulates at least portions of the semiconductor chips and the dummy chip. An upper surface of the wiring portion is disposed below a center line of the fan-out semiconductor package, and the thickness t of the dummy chip is such that T/2?t?3T/2 in which T is a distance from the upper surface of the wiring portion to the center line of the fan-out semiconductor package.

Abstract: A method of fabricating a semiconductor device including a diffused metal-oxide-semiconductor (DMOS) transistor, an n-type metal-oxide-semiconductor (NMOS) transistor, and a p-type metal-oxide-semiconductor (PMOS) transistor includes forming separation regions in a semiconductor substrate, forming a gate insulating film, forming a DMOS gate electrode on the gate insulating film, forming a first mask pattern on the semiconductor substrate, performing a first ion implantation process, forming a second mask pattern on the semiconductor substrate, performing a second ion implantation process, forming a third mask pattern on the semiconductor substrate and performing a third ion implantation process into the semiconductor substrate, and forming a fourth mask pattern on the semiconductor substrate and performing a fourth ion implantation process.

Abstract: An image sensor according to some example embodiments includes a pixel array unit including a plurality of transmission signal lines and a plurality of output signal lines, and a plurality of pixels connected to the plurality of transmission signal lines and the plurality of output signal lines. Each of the plurality of pixels includes a plurality of photoelectric conversion elements, which are configured to detect and photoelectrically convert incident light. The plurality of pixels include at least one autofocusing pixel and at least one normal pixel.

Abstract: A fan-out semiconductor package includes a wiring portion, semiconductor chips, a dummy chip, and an encapsulant. The wiring portion includes an insulating layer, conductive patterns formed on the insulating layer, and conductive vias penetrating through the insulating layer and connected to the conductive patterns. The semiconductor chips are disposed on one region of the wiring portion, and the dummy chip is disposed on another region thereof and has a thickness smaller than those of the semiconductor chips. The encapsulant encapsulates at least portions of the semiconductor chips and the dummy chip. An upper surface of the wiring portion is disposed below a center line of the fan-out semiconductor package, and the thickness t of the dummy chip is such that T/2?t?3T/2 in which T is a distance from the upper surface of the wiring portion to the center line of the fan-out semiconductor package.

Abstract: A semiconductor package includes a wiring portion including an insulating layer, conductive patterns disposed on the insulating layer, and conductive vias penetrating through the insulating layer and connected to the conductive patterns, a semiconductor chip disposed on the wiring portion, an encapsulant disposed on the wiring portion and encapsulating at least a portion of the semiconductor chip, and a metal layer disposed on the semiconductor chip and the encapsulant and having a thickness of 10 ?m to 70 ?m.

Abstract: A method for measurement of an information-security-controlling status in accordance with the present disclosure includes receiving actual inspection data obtained by actually inspecting whether each domain complies with each security-controlling item, computing security-controlling status measurement scores for each domain on the basis of a significance grade of each control item, the degree of compliance with a corresponding control item, and a weighting set by a measurement manager, computing a final security-controlling status measurement score for a parent organization to which each domain belongs on the basis of an average of the security-controlling status measurement scores for each domain, and outputting the computed security-controlling status measurement scores and final security-controlling status measurement score.

Abstract: Provided are a method of detecting abnormal financial transactions and an apparatus thereof. The apparatus includes: a memory in which an abnormal transaction detection program is stored; and a processor configured to execute the program. Upon execution of the program, the processor performs a data preprocessing operation to acquired payment data, extracts at least one feature adaptively determined in advance from results of the preprocessing operation, and uses the extracted feature to determine whether the payment data correspond to an abnormal transaction through a machine learning algorithm adaptively determined in advance.

Abstract: An integrated semiconductor device includes a first transistor and a second transistor formed on a semiconductor substrate, and an isolation structure located adjacent to the transistors, including deep trenches, trapping regions formed between the deep trenches, and trench bottom doping regions formed at the end of each of the deep trenches, wherein each of the trapping regions includes a buried layer, a well region formed on the buried layer, and a highly doped region formed on the well region.

Abstract: A fan-out semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, an encapsulant sealing at least a portion of the inactive surface, a first connection member disposed on the active surface and including a redistribution layer and a first via electrically connecting the connection pad to the redistribution layer, a passivation layer disposed on the first connection member, and an under-bump metal layer including an external connection pad disposed on the passivation layer and a second via connecting the external connection pad to the redistribution layer. In a vertical direction, the first and second vias are disposed within the external connection pad and do not overlap each other.

Abstract: Image sensors are provided. The image sensors may include a substrate including first, second, third and fourth regions, a first photoelectric conversion element in the first region, a second photoelectric conversion element in the second region, a third photoelectric conversion element in the third region, a fourth photoelectric conversion element in the fourth region, a first microlens at least partially overlapping both the first and second photoelectric conversion elements, and a second microlens at least partially overlapping both the third and fourth photoelectric conversion elements. The image sensors may also include a floating diffusion region and first, second and third pixel transistors configured to perform different functions from each other. Each of the first, second and third pixel transistors may be disposed in at least one of first, second, third and fourth pixel regions. The first pixel transistor may include multiple first pixel transistors.

Abstract: An integrated semiconductor device includes a first transistor and a second transistor formed on a semiconductor substrate, and an isolation structure located adjacent to the transistors, including deep trenches, trapping regions formed between the deep trenches, and trench bottom doping regions formed at the end of each of the deep trenches, wherein each of the trapping regions includes a buried layer, a well region formed on the buried layer, and a highly doped region formed on the well region.

Abstract: An image sensor and a method for fabricating the same are provided, in which the image sensor includes a substrate including a first sensing region having a photoelectric device therein, a boundary isolation film partitioning the first sensing region, an inner reflection pattern film within the substrate in the sensing region, an infrared filter on the substrate, and a micro lens on the infrared filter.

Abstract: An image sensor may optimize control of each pixel and/or each photodiode therein according to various pixel structures therein. An electronic apparatus may include the image sensor. The image sensor may include a plurality of pixels, each including a photodiode and a transfer transistor configured to transfer charges accumulated in the photodiode to a floating diffusion floating diffusion region, and transfer transistor lines respectively connected to gate electrodes of the transfer transistors of the pixels. The transfer transistor lines may receive voltages having different magnitudes.