Abstract: Disclosed are novel compounds of Chemical Formula 1, optical isomers of the compounds, and pharmaceutically acceptable salts of the compounds or the optical isomers. The compounds, isomers, and salts exhibit excellent activity as GLP-1 receptor agonists. In particular, they, as GLP-1 receptor agonists, exhibit excellent glucose tolerance, thus having a great potential to be used as therapeutic agents for metabolic diseases. Moreover, they exhibit excellent pharmacological safety for cardiovascular systems.

Abstract: A method for operating a memory includes determining to perform an error correction operation; determining whether to perform an error correction operation; generating an internal address when the error correction operation is performed; reading data from memory cells that are selected based on the internal address and an error correction code corresponding to the data; performing an error correction operation on the data based on the error correction code to produce an error-corrected data; writing the error-corrected data and an error correction code corresponding to the error-corrected data into the memory cells; determining one or more regions among regions in the memory as a repair-requiring region based on an error detected when the error correction operation is performed; receiving a first command; backing up the data and the error correction code into a redundant region in response to the first command; and repairing the repair-requiring region with the redundant region.

Abstract: A method for operating a memory includes determining to perform an error correction operation; determining whether to perform an error correction operation; generating an internal address when the error correction operation is performed; reading data from memory cells that are selected based on the internal address and an error correction code corresponding to the data; performing an error correction operation on the data based on the error correction code to produce an error-corrected data; writing the error-corrected data and an error correction code corresponding to the error-corrected data into the memory cells; determining one or more regions among regions in the memory as a repair-requiring region based on an error detected when the error correction operation is performed; receiving a first command; backing up the data and the error correction code into a redundant region in response to the first command; and repairing the repair-requiring region with the redundant region.

Abstract: A memory system may include a controller; and a plurality of memory modules, wherein a data input and output of the plurality of memory modules is performed with a single channel manner according to an address signal provided from the controller in common, wherein each of the plurality of memory modules includes a buffer chip and a plurality of memory chips coupled to the buffer chip, wherein all the buffer chips of the plurality of memory modules are directly coupled to the controller through independent input and output bus.

Abstract: A method for operating a memory includes determining to perform an error correction operation; determining whether to perform an error correction operation; generating an internal address when the error correction operation is performed; reading data from memory cells that are selected based on the internal address and an error correction code corresponding to the data; performing an error correction operation on the data based on the error correction code to produce an error-corrected data; writing the error-corrected data and an error correction code corresponding to the error-corrected data into the memory cells; determining one or more regions among regions in the memory as a repair-requiring region based on an error detected when the error correction operation is performed; receiving a first command; backing up the data and the error correction code into a redundant region in response to the first command; and repairing the repair-requiring region with the redundant region.

Abstract: A semiconductor device includes a delay-locked clock generation circuit configured to generate a delay-locked clock which is driven by at least one internal clock selected from a plurality of internal clocks in response to a phase control signal. The semiconductor device also includes a latency command generation circuit configured to generate a latency command for generating transmission data from data by latching an internal command sequentially by the at least one internal clock in response to the phase control signal and shifting the sequentially latched internal command by a period set by a shifting control signal in response to the delay-locked clock.

Abstract: A semiconductor device includes a delay-locked clock generation circuit configured to generate a delay-locked clock which is driven by at least one internal clock selected from a plurality of internal clocks in response to a phase control signal. The semiconductor device also includes a latency command generation circuit configured to generate a latency command for generating transmission data from data by latching an internal command sequentially by the at least one internal clock in response to the phase control signal and shifting the sequentially latched internal command by a period set by a shifting control signal in response to the delay-locked clock.

Abstract: An internal clock generation circuit includes an interpolation clock generation circuit and a locked clock generation circuit. The interpolation clock generation circuit generates an interpolation clock signal from a division clock signal in response to a switching control signal and a current control signal. The locked clock generation circuit includes an oscillator and generates a locked clock signal for generating an internal clock signal from the interpolation clock signal.

Abstract: A memory system may include a controller; and a plurality of memory modules, wherein a data input and output of the plurality of memory modules is performed with a single channel manner according to an address signal provided from the controller in common, wherein each of the plurality of memory modules includes a buffer chip and a plurality of memory chips coupled to the buffer chip, wherein all the buffer chips of the plurality of memory modules are directly coupled to the controller through independent input and output bus.

Abstract: A semiconductor device includes a first mode signal generation circuit suitable for generating a first mode signal in response to a command, the first mode signal being enabled in the case where a first period determined depending on a current characteristic of a first MOS transistor is longer than a second period determined by a first passive element; and a second mode signal generation circuit suitable for generating a second mode signal in response to the command, the second mode signal being enabled in the case where a third period determined by a second passive element is longer than a fourth period determined depending on a current characteristic of a second MOS transistor.

Abstract: A memory device includes: a plurality of bank groups each comprising one or more banks; a first bus coupled to the plurality of bank groups; a second bus coupled to the plurality of bank groups; a toggle signal generation unit suitable for generating a first signal which toggles in response to a column command signal and a second signal having the opposite logic value of the first signal; a column command transmission unit suitable for transmitting a read command signal or write command signal to the first bus when the first signal is activated, and transmitting the read command signal or write command signal to the second bus when the second signal is activated; and a column address transmission unit suitable for transmitting one or more column address signals corresponding to the read command signal or write command signal to a bus to which the read command signal or write command signal is transmitted, between the first and second buses.

Abstract: A semiconductor device includes a first mode signal generation circuit suitable for generating a first mode signal in response to a command, the first mode signal being enabled in the case where a first period determined depending on a current characteristic of a first MOS transistor is longer than a second period determined by a first passive element; and a second mode signal generation circuit suitable for generating a second mode signal in response to the command, the second mode signal being enabled in the case where a third period determined by a second passive element is longer than a fourth period determined depending on a current characteristic of a second MOS transistor.

Abstract: An internal clock generation circuit includes an interpolation clock generation circuit and a locked clock generation circuit. The interpolation clock generation circuit generates an interpolation clock signal from a division clock signal in response to a switching control signal and a current control signal. The locked clock generation circuit includes an oscillator and generates a locked clock signal for generating an internal clock signal from the interpolation clock signal.

Abstract: A memory device includes: a plurality of bank groups each comprising one or more banks; a first bus coupled to the plurality of bank groups; a second bus coupled to the plurality of bank groups; a toggle signal generation unit suitable for generating a first signal which toggles in response to a column command signal and a second signal having the opposite logic value of the first signal; a column command transmission unit suitable for transmitting a read command signal or write command signal to the first bus when the first signal is activated, and transmitting the read command signal or write command signal to the second bus when the second signal is activated; and a column address transmission unit suitable for transmitting one or more column address signals corresponding to the read command signal or write command signal to a bus to which the read command signal or write command signal is transmitted, between the first and second buses.

Abstract: A semiconductor apparatus includes a plurality of dies. Any one of the dies may be set to a first rank and another of the dies may be set to a second rank. One or more of the first and second ranks may be configured to output any one of an even-numbered byte and an odd-numbered byte through an input/output stage at a timing earlier than the other one, according to a read command.

Abstract: A memory device includes: a plurality of bank groups each comprising one or more banks; a first bus coupled to the plurality of bank groups; a second bus coupled to the plurality of bank groups; a toggle signal generation unit suitable for generating a first signal which toggles in response to a column command signal and a second signal having the opposite logic value of the first signal; a column command transmission unit suitable for transmitting a read command signal or write command signal to the first bus when the first signal is activated, and transmitting the read command signal or write command signal to the second bus when the second signal is activated; and a column address transmission unit suitable for transmitting one or more column address signals corresponding to the read command signal or write command signal to a bus to which the read command signal or write command signal is transmitted, between the first and second buses.

Abstract: A semiconductor device may be provided. The semiconductor device may include an input information signal generation circuit and a command generation circuit. The input information signal generation circuit may be configured to latch a command in synchronization with a point of time that a division clock signal is inputted. The command generation circuit may be configured to shift a phase of the latched command in synchronization with a multiplication clock signal to shift the command.

Abstract: Disclosed herein is a stacked memory device including a base die and a plurality of core dies stacked using a plurality of through-chip electrodes. Each of the core dies may include a plurality of input pads capable of receiving addresses externally in a wafer-level test mode; a control signal generation unit capable of decoding the addresses received through the input pads to generate a first control signal; an address generation unit capable of generating a first address based on the addresses received through the input pads; and a signal selection unit capable of selecting one of the first control signal and a second control signal received from the base die through a corresponding through-chip electrode to output a global control signal, and selecting one of the first address and a second address received from the base die through a corresponding through-chip electrode to output a global address.

Abstract: A memory system may include a controller and a plurality of memory modules. Each of the plurality of memory modules may include a buffer chip and a plurality of memory chips coupled to the buffer chip through independent input and output (I/O) lines. The buffer chips in the plurality of memory modules may be coupled to the controller through independent I/O buses and may be configured to control data I/O operations of the plurality of memory modules and the controller.

Abstract: A semiconductor apparatus includes a plurality of dies. Any one of the dies may be set to a first rank and another of the dies may be set to a second rank. One or more of the first and second ranks may be configured to output any one of an even-numbered byte and an odd-numbered byte through an input/output stage at a timing earlier than the other one, according to a read command.