Abstract: An internal voltage generating circuit of a semiconductor memory apparatus includes a first voltage generating unit to output a first output voltage to a common node, the first output voltage is generated in response to a first reference voltage, and a second voltage generating unit to output a second output voltage to the common node, the second output voltage is generated in response to a second reference voltage.

Abstract: A semiconductor memory device can stably supply a high voltage even if not only the PVT (Process, Voltage, and Temperature) fluctuations but also the level fluctuations of the external voltage are caused by the variation of the external environments. The driving force of a standby VPP generating unit and a plurality of active VPP generating units are changed according to the PVT fluctuations.

Abstract: On-die termination control circuit of semiconductor memory device includes a counter configured to count an external clock to output a first code, and to count an internal clock to output a second code, a transfer controller configured to determine whether to transfer the first code and the second code in response to a first termination command and a normal termination controller configured to compare the first code and the second code with each other to determine enabling/disabling timings of a termination operation in response to a second termination command.

Abstract: A high voltage generator includes: a high voltage detecting unit for detecting a level of a high voltage and outputting a high enable signal; an auto refresh control unit for enabling an auto refresh high enable signal in response to a detection signal enabled when a level of a power supplying voltage is lower than a certain level and in response to the pumping enable signal during an auto refresh operation; and a high voltage generating unit for generating a high voltage by performing a pumping operation in response to the auto refresh pumping enable signal.

Abstract: A semiconductor memory device can ensure a sufficient margin between a column select signal and a column address signal when a delay time of the column select signal is increased to improve an address access time during a write operation. The semiconductor memory device includes a discrimination signal generating circuit configured to generate a discrimination signal activated in a write operation of the device, and a selective delay circuit configured to selectively delay a column address in response to the discrimination signal.

Abstract: A semiconductor memory device adjusts an activation timing and pulse width of a pin strobe signal according to a power supply voltage variation, and thereby loads data on a pipelatch properly and prevents an activation period of a pin strobe signal from falling out of a period for valid data. The semiconductor memory device includes a voltage detector configured to detect a level of a power supply voltage to output a detection signal, a pin strobe signal transfer path configured to transfer a pin strobe signal determining an input timing of data to a pipelatch, a delay controller configured to control a delay value of the pin strobe signal transfer path in response to the detection signal, and a pulse width modulator configured to modulate a pulse width of the pin strobe signal in response to the detection signal.

Abstract: A termination impedance control circuit is capable of controlling a dynamic ODT operation in a DDR3-level semiconductor memory device. The termination impedance control circuit includes a counter unit configured to count an external clock and an internal clock to output a first code and a second code, respectively, and a dynamic controller configured to enable a dynamic termination operation by comparing the first code with the second code in response to a write command and disable the dynamic termination operation after a predetermined time, determined according to a burst length, has lapsed after the dynamic termination operation is enabled.

Abstract: A semiconductor memory device is effectively able to adjust operation time for on-die termination (ODT). The semiconductor memory device includes a latency control unit, a control signal generating unit, a trimming control unit, and a termination circuit. The latency control unit produces an ODT driving enable signal by delaying an ODT operation signal from an external circuit during a predetermined latency. The control signal generating unit produces control signals to control a change of waveform of the ODT driving enable signal. The trimming control unit changes the waveform of the ODT driving enable signal in response to the control signals, thereby outputting a ODT driving signal. The termination circuit connects a termination resistance to an impedance adjusting node in response to the ODT driving signal.

Abstract: A semiconductor memory device having read and write operations includes a discrimination signal generating unit for generating a discrimination signal during the write operation; and a selective delay unit for receiving and selectively delaying a command-group signal in response to the discrimination signal.

Abstract: A delay selection circuit for use in a semiconductor memory device prevents a tAA from increasing at a read operation due to a delayed command type of signal. The delay selection circuit includes a delay line unit, a power supply voltage detection unit and a path selection unit. The delay line unit has two delay lines for delaying a command type of signal by different delay amounts. The power supply voltage detection unit detects a voltage level of a power supply voltage. The path selection unit selects one of each output of the two delay lines according to an output of the power supply voltage detection unit.

Abstract: The internal voltage generator of a semiconductor integrated circuit includes at least one variable reference voltage generating unit that generates a base reference voltage increased or decreased according to the variation in temperature, at least one level shifting unit that transforms the base reference voltage outputted by the at least one variable reference voltage generating unit into at least one prescribed reference voltage for generating internal voltage and outputs the transformed reference voltage, and at least one internal voltage generating unit that generates an internal voltage by using the at least one reference voltage for generating internal voltage outputted by the at least one level shifting unit.

Abstract: A semiconductor memory device is capable of stably securing an on-die-termination (ODT) latency in spite of PVT variations and various operating speeds. The semiconductor memory device includes a plurality of termination resistors connected to an output pad in series and parallel, a drive controller, a delay path, and a delay control signal generator. The drive controller activates/inactivates the plurality of termination resistors in response to a driving control signal. The delay path delays a termination command by a delay time corresponding to an on-die-termination (ODT) latency to output the driving control signal, wherein the termination command is converted into a delay locked loop (DLL) clock domain signal. The delay control signal generator controls a conversion point of the termination command into the DLL clock domain signal.

Abstract: A semiconductor memory device is provided to improve the tAA characteristics. The semiconductor memory device includes: a discrimination signal generating unit for generating a first discrimination signal denoting a write operation of the semiconductor memory device; a selective delay unit for delaying a command-group signal in response to a second discrimination signal; and a fuse unit for generating the second discrimination signal based on the first discrimination signal, the second discrimination signal determining whether the selective delay unit selectively delays the command-group signal in response to the first discrimination signal.

Abstract: Provided are a core voltage generator and a method for generating a core voltage in a semiconductor memory device. The core voltage generator includes a first discharge driver for discharging a core voltage terminal for an interval at which the voltage is higher than a target level, in response to a first enable signal activated for a first predetermined period after overdriving a bit line, and a second discharge driver for discharging the core voltage terminal for an interval at which the voltage at the core voltage terminal is higher than the target level by a predetermined threshold, in response to a second enable signal activated for a second predetermined period after overdriving the bit line, wherein the second predetermined period is shorter than the first predetermined period.

Abstract: The internal voltage generator of a semiconductor integrated circuit includes at least one variable reference voltage generating unit that generates a base reference voltage increased or decreased according to the variation in temperature, at least one level shifting unit that transforms the base reference voltage outputted by the at least one variable reference voltage generating unit into at least one prescribed reference voltage for generating internal voltage and outputs the transformed reference voltage, and at least one internal voltage generating unit that generates an internal voltage by using the at least one reference voltage for generating internal voltage outputted by the at least one level shifting unit.

Abstract: A semiconductor memory device is effectively able to adjust operation time for on-die termination (ODT). The semiconductor memory device includes a latency control unit, a control signal generating unit, a trimming control unit, and a termination circuit. The latency control unit produces an ODT driving enable signal by delaying an ODT operation signal from an external circuit during a predetermined latency. The control signal generating unit produces control signals to control a change of waveform of the ODT driving enable signal. The trimming control unit changes the waveform of the ODT driving enable signal in response to the control signals, thereby outputting a ODT driving signal. The termination circuit connects a termination resistance to an impedance adjusting node in response to the ODT driving signal.

Abstract: A memory device includes a delay circuit and a delay selection unit. The delay circuit delays a pulse signal to generate a delayed pulse signal. The pulse signal is used to generate a write enable signal and a read enable signal. The delay selection unit selects one of the delayed pulse signal output from the delay circuit in a test mode and the pulse signal in a normal mode.

Abstract: A delay selection circuit for use in a semiconductor memory device prevents a tAA from increasing at a read operation due to a delayed command type of signal. The delay selection circuit includes a delay line unit, a power supply voltage detection unit and a path selection unit. The delay line unit has two delay lines for delaying a command type of signal by different delay amounts. The power supply voltage detection unit detects a voltage level of a power supply voltage. The path selection unit selects one of each output of the two delay lines according to an output of the power supply voltage detection unit.

Abstract: A semiconductor memory device can stably supply a high voltage even if not only the PVT (Process, Voltage, and Temperature) fluctuations but also the level fluctuations of the external voltage are caused by the variation of the external environments. The driving force of a standby VPP generating unit and a plurality of active VPP generating units are changed according to the PVT fluctuations.

Abstract: There is provided a multi-port memory device, which is capable of preventing a first high data fail phenomenon at an initial operation in a current sensing type global data bus transmission/reception structure without causing a problem in a low data transmission. In the multi-port memory device having a data transmission/reception block (bank, port, global data bus connection block, etc.) which exchanges data with the global data bus in a current sensing type data transmission/reception structure, an initialization switch is used to discharge each global data bus line and an initialization signal generator controls the initialization switch. A first high data fail at the initial operation is caused by a high precharge level of the global data bus. According to the present invention, it is possible to lower a high precharge level without causing a problem in data transmission.