Patents by Inventor Laertis Economikos

Laertis Economikos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200161296
    Abstract: A method of forming a gate cut isolation, a related structure and IC are disclosed. The method forms a dummy gate material mandrel having a sidewall positioned between and spaced from a first active region covered by the mandrel and a second active region not covered by the mandrel. A gate cut dielectric layer is formed against the sidewall of the mandrel, and may be trimmed. A dummy gate material may deposited to encase the remaining gate cut dielectric layer. Subsequent dummy gate formation and replacement metal gate processing forms a gate conductor with the gate cut isolation electrically isolating respective first and second portions of the gate conductor. The method creates a very thin, slightly non-vertical gate cut isolation, and eliminates the need to define a gate cut critical dimension or fill a small gate cut opening.
    Type: Application
    Filed: November 19, 2018
    Publication date: May 21, 2020
    Inventors: Hui Zang, Laertis Economikos, Ruilong Xie
  • Publication number: 20200152518
    Abstract: Methods of forming cross-coupling contacts for field-effect transistors and structures for field effect-transistors that include cross-coupling contacts. A dielectric cap is formed over a gate structure and a sidewall spacer adjacent to a sidewall of the gate structure. A portion of the dielectric cap is removed from over the sidewall spacer and the gate structure to expose a first portion of the gate electrode of the gate structure at a top surface of the gate structure. The sidewall spacer is then recessed relative to the gate structure to expose a portion of the gate dielectric layer at the sidewall of the gate structure, which is removed to expose a second portion of the gate electrode of the gate structure. A cross-coupling contact is formed that connects the first and second portions of the gate electrode of the gate structure with an epitaxial semiconductor layer adjacent to the sidewall spacer.
    Type: Application
    Filed: November 9, 2018
    Publication date: May 14, 2020
    Inventors: Hui Zang, Ruilong Xie, Chanro Park, Laertis Economikos
  • Publication number: 20200152509
    Abstract: A semiconductor device includes one or more fins extending from a substrate, the one or more fins having source/drain epitaxial grown material (S/D epitaxy) thereon that merges one or more fins, a gate formed over the one or more fins, the gate including high k metal gate disposed between gate spacers and a metal liner over the S/D epitaxy and sides of the gate spacers. The gate includes a self-aligned contact cap over the HKMG and the metal liner.
    Type: Application
    Filed: November 8, 2018
    Publication date: May 14, 2020
    Inventors: Andrew Greene, Ruilong Xie, Laertis Economikos, Veeraraghavan S. Basker, Chanro Park, Hui Zang
  • Publication number: 20200135473
    Abstract: One integrated circuit product disclosed herein includes a first final gate structure for a first transistor device, a second final gate structure for a second transistor device, wherein the first and second transistor devices have a gate width that extends in a gate width direction and a gate length that extends in a gate length direction, and a gate separation structure positioned between the first and second final gate structures, the gate separation structure comprising at least one insulating material. The gate separation structure further has a substantially uniform width in the gate width direction for substantially an entire vertical height of the gate separation structure and a first side surface and a second side surface, wherein an end surface of the first final gate structure contacts the first side surface and an end surface of the second final gate structure contacts the second side surface.
    Type: Application
    Filed: November 11, 2019
    Publication date: April 30, 2020
    Inventors: Chanro Park, Ruilong Xie, Hui Zang, Laertis Economikos, Andre LaBonte
  • Publication number: 20200111713
    Abstract: Processes form integrated circuit apparatuses that include parallel fins, wherein the fins are patterned in a first direction. Parallel gate structures intersect the fins in a second direction perpendicular to the first direction, wherein the gate structures have a lower portion adjacent to the fins and an upper portion distal to the fins. Source/drain structures are positioned on the fins between the gate structures. Source/drain contacts are positioned on the source/drain structures and multiple insulator layers are positioned between the gate structures and the source/drain contacts. Additional upper sidewall spacers are positioned between the upper portion of the gate structures and the multiple insulator layers.
    Type: Application
    Filed: October 3, 2018
    Publication date: April 9, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Laertis Economikos, Shesh Mani Pandey, Chanro Park, Ruilong Xie
  • Publication number: 20200091143
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate cut structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and drain regions and sidewall spacers comprised of different dielectric materials; and contacts connecting to the source and drain regions and isolated from the gate structures by the different dielectric materials.
    Type: Application
    Filed: September 18, 2018
    Publication date: March 19, 2020
    Inventors: Hui ZANG, Ruilong XIE, Laertis ECONOMIKOS
  • Publication number: 20200083363
    Abstract: A device including oxide spacer in a contact over active gates (COAG) and method of production thereof. Embodiments include first gate structures over a fin of a substrate and second gate structures, each over an outer portion of the fin and a shallow trench isolation (STI) layer adjacent to the fin; a first raised source/drain (RSD) in a portion of the fin between the first gate structures and a second RSD in the portion of the fin between the first and second gate structures; a metal liner over the first and second RSD and on sidewall portions of the first and second gate structures; a metal layer over the metal liner; and an interlayer dielectric (ILD) over the metal liner and portions of the first and second gate structures.
    Type: Application
    Filed: September 10, 2018
    Publication date: March 12, 2020
    Inventors: Hui ZANG, Laertis ECONOMIKOS, Jiehui SHU, Ruilong XIE
  • Patent number: 10586860
    Abstract: In conjunction with a replacement metal gate (RMG) process for forming a fin field effect transistor (FinFET), gate isolation methods and associated structures leverage the formation of distinct narrow and wide gate cut regions in a sacrificial gate. The formation of a narrow gate cut between closely-spaced fins can decrease the extent of etch damage to interlayer dielectric layers located adjacent to the narrow gate cut by delaying the deposition of such dielectric layers until after formation of the narrow gate cut opening. The methods and resulting structures also decrease the propensity for short circuits between later-formed, adjacent gates.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: March 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jiehui Shu, Laertis Economikos, Xusheng Wu, John Zhang, Haigou Huang, Hui Zhan, Tao Han, Haiting Wang, Jinping Liu, Hui Zang
  • Publication number: 20200075738
    Abstract: This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor substrate having a first fin and a second fin spaced from the first fin; a first source/drain region in the first fin, the first source/drain region encompassing a top surface and two opposing lateral sides of the first fin; a second source/drain region in the second fin, the second source/drain encompassing a top surface and two opposing lateral sides of the second fin; and a metal contact extending over the first source/drain region and the second source/drain region and surrounding the top surface and at least a portion of the two opposing lateral sides of each of the first and the second source/drain regions.
    Type: Application
    Filed: September 4, 2018
    Publication date: March 5, 2020
    Inventors: Hui Zang, Ruilong Xie, Shesh M. Pandey, Laertis Economikos
  • Patent number: 10580685
    Abstract: A methodology for forming a fin field effect transistor (FinFET) includes the co-integration of various isolation structures, including gate cut and shallow diffusion break isolation structures that are formed with common masking and etching steps. Following an additional patterning step to provide segmentation for source/drain conductive contacts, a single deposition step is used to form an isolation dielectric layer within each of gate cut openings, shallow diffusion break openings and cavities over shallow trench isolation between device active areas.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: March 3, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Haiting Wang, Hong Yu, Laertis Economikos
  • Publication number: 20200066899
    Abstract: A transistor device disclosed herein includes, among other things, a gate electrode positioned above a semiconductor material region, a sidewall spacer positioned adjacent the gate electrode, a gate insulation layer having a first portion positioned between the gate electrode and the semiconductor material region and a second portion positioned between a lower portion of the sidewall spacer and the gate electrode along a portion of a sidewall of the gate electrode, an air gap cavity located between the sidewall spacer and the gate electrode and above the second portion of the gate insulation layer, and a gate cap layer positioned above the gate electrode, wherein the gate cap layer seals an upper end of the air gap cavity so as to define an air gap positioned adjacent the gate electrode.
    Type: Application
    Filed: October 25, 2019
    Publication date: February 27, 2020
    Inventors: Laertis Economikos, Shesh Mani Pandey, Hui Zang, Haiting Wang, Jinping Liu
  • Patent number: 10573753
    Abstract: A device including oxide spacer in a contact over active gates (COAG) and method of production thereof. Embodiments include first gate structures over a fin of a substrate and second gate structures, each over an outer portion of the fin and a shallow trench isolation (STI) layer adjacent to the fin; a first raised source/drain (RSD) in a portion of the fin between the first gate structures and a second RSD in the portion of the fin between the first and second gate structures; a metal liner over the first and second RSD and on sidewall portions of the first and second gate structures; a metal layer over the metal liner; and an interlayer dielectric (ILD) over the metal liner and portions of the first and second gate structures.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: February 25, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Laertis Economikos, Jiehui Shu, Ruilong Xie
  • Patent number: 10566201
    Abstract: A method that includes forming a conductive source/drain structure that is conductively coupled to source/drain regions of first and second transistor devices, selectively forming a conductive source/drain metallization cap structure on and in contact with an upper surface of the conductive source/drain structure, forming a patterned etch mask that exposes a portion of the gate cap and a portion of the conductive source/drain metallization cap structure, and performing at least one etching process to remove the exposed portion of the gate cap and thereafter an exposed portion of the final gate structure so as to form a gate cut opening, wherein the conductive source/drain metallization cap structure protects the underlying conductive source/drain structure during the at least one etching process.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: February 18, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Chanro Park, Ruilong Xie, Hui Zang, Laertis Economikos, Andre LaBonte
  • Publication number: 20200052106
    Abstract: At least one method, apparatus, and system providing semiconductor devices comprising a first gate having a first width and comprising a first work function metal (WFM); a first liner disposed over the first WFM; a first gate metal having a first height; and a first pinch-off spacer over the first WFM, the first liner, and the first gate metal to above the first height; and a second gate having a second width greater than the first width, and comprising a second WFM; a second liner disposed over the second WFM; a second gate metal having substantially the first height; and a first conformal spacer over the second WFM and the second liner.
    Type: Application
    Filed: August 10, 2018
    Publication date: February 13, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Laertis Economikos, Hui Zang, Ruilong Xie, Neal Makela, Pei Liu, Jiehui Shu, Chih-chiang Chang
  • Publication number: 20200044034
    Abstract: The disclosure relates to methods of forming integrated circuit (IC) structures with a metal cap on a cobalt layer for source and drain regions of a transistor. An integrated circuit (IC) structure according to the disclosure may include: a semiconductor fin on a substrate; a gate structure over the substrate, the gate structure having a first portion extending transversely across the semiconductor fin; an insulator cap positioned on the gate structure above the semiconductor fin; a cobalt (Co) layer on the semiconductor fin adjacent to the gate structure, wherein an upper surface of the Co layer is below an upper surface of the gate structure; and a metal cap on the Co layer.
    Type: Application
    Filed: August 3, 2018
    Publication date: February 6, 2020
    Inventors: Laertis Economikos, Kevin J. Ryan, Ruilong Xie, Hui Zang
  • Patent number: 10553486
    Abstract: Disclosed is a method of forming an integrated circuit (IC) and the resulting structure. The method includes forming a transistor with a sacrificial gate on a channel region, a gate sidewall spacer on the sacrificial gate, and sacrificial plugs on the source/drain regions. The sacrificial gate is replaced with a gate, a gate cap on the gate, and a sacrificial cap on the gate cap and the gate sidewall spacer (which was recessed). Thus, top surfaces of the gate cap and gate sidewall spacer are at a lower level than the top surfaces of the sacrificial plugs and, when the sacrificial plugs are replaced with metal plugs, the gate cap is protected. In the resulting structure, the gate cap has a desired thickness and the top surface of the gate cap is at a lower level than the top surfaces of the metal plugs to reduce the risk of shorts.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: February 4, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Ruilong Xie, Laertis Economikos
  • Patent number: 10553698
    Abstract: At least one method, apparatus and system disclosed herein involves adjusting for a misalignment of a gate cut region with respect to semiconductor processing. A plurality of fins are formed on a semiconductor substrate. A gate region is formed over a portion of the fins. The gate region comprises a first dummy gate and a second dummy gate. A gate cut region is formed over the first dummy gate. A conformal fill material is deposited into the gate cut region. At least one subsequent processing step is performed.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: February 4, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Laertis Economikos, Ruilong Xie
  • Publication number: 20200035555
    Abstract: Disclosed is a method of forming an integrated circuit (IC) and the resulting structure. The method includes forming a transistor with a sacrificial gate on a channel region, a gate sidewall spacer on the sacrificial gate, and sacrificial plugs on the source/drain regions. The sacrificial gate is replaced with a gate, a gate cap on the gate, and a sacrificial cap on the gate cap and the gate sidewall spacer (which was recessed). Thus, top surfaces of the gate cap and gate sidewall spacer are at a lower level than the top surfaces of the sacrificial plugs and, when the sacrificial plugs are replaced with metal plugs, the gate cap is protected. In the resulting structure, the gate cap has a desired thickness and the top surface of the gate cap is at a lower level than the top surfaces of the metal plugs to reduce the risk of shorts.
    Type: Application
    Filed: July 27, 2018
    Publication date: January 30, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Ruilong Xie, Laertis Economikos
  • Publication number: 20200035543
    Abstract: A methodology for forming a fin field effect transistor (FinFET) includes the co-integration of various isolation structures, including gate cut and shallow diffusion break isolation structures that are formed with common masking and etching steps. Following an additional patterning step to provide segmentation for source/drain conductive contacts, a single deposition step is used to form an isolation dielectric layer within each of gate cut openings, shallow diffusion break openings and cavities over shallow trench isolation between device active areas.
    Type: Application
    Filed: July 27, 2018
    Publication date: January 30, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Hui ZANG, Haiting WANG, Hong YU, Laertis ECONOMIKOS
  • Patent number: 10546853
    Abstract: A device including RM below the top surface of an HKMG structure, and method of production thereof. Embodiments include first and second HKMG structures over a portion of the substrate and on opposite sides of the STI region, the first and second HKMG structures having a top surface; and a RM over the STI region and between the first and second HKMG structures, wherein the RM is below the top surface of the first and second HKMG structures.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: January 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Laertis Economikos, Hui Zang, Ruilong Xie