Patents by Inventor Laertis Economikos

Laertis Economikos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10998422
    Abstract: At least one method, apparatus and system disclosed herein involves adjusting for a misalignment of a gate cut region with respect to semiconductor processing. A plurality of fins are formed on a semiconductor substrate. A gate region is formed over a portion of the fins. The gate region comprises a first dummy gate and a second dummy gate. A gate cut region is formed over the first dummy gate. A conformal fill material is deposited into the gate cut region. At least one subsequent processing step is performed.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: May 4, 2021
    Inventors: Hui Zang, Laertis Economikos, Ruilong Xie
  • Patent number: 10937786
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate cut structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and drain regions and sidewall spacers comprised of different dielectric materials; and contacts connecting to the source and drain regions and isolated from the gate structures by the different dielectric materials.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: March 2, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Hui Zang, Ruilong Xie, Laertis Economikos
  • Patent number: 10923469
    Abstract: An integrated circuit (IC) includes an active area including at least one active fin-type field effect transistor (FinFET), and a trench isolation adjacent to the active area. At least one inactive gate is positioned over the trench isolation. A vertically extending resistor body is positioned adjacent the at least one inactive gate over the trench isolation. A lower end of the resistor is below an upper surface of the trench isolation. The resistor reduces interconnect layer thickness to improve yield, and significantly reduces resistor footprint to enable scaling.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: February 16, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Hui Zang, Guowei Xu, Jiehui Shu, Ruilong Xie, Yurong Wen, Garo J. Derderian, Shesh M. Pandey, Laertis Economikos
  • Patent number: 10879073
    Abstract: One integrated circuit product disclosed herein includes a first final gate structure for a first transistor device, a second final gate structure for a second transistor device, wherein the first and second transistor devices have a gate width that extends in a gate width direction and a gate length that extends in a gate length direction, and a gate separation structure positioned between the first and second final gate structures, the gate separation structure comprising at least one insulating material. The gate separation structure further has a substantially uniform width in the gate width direction for substantially an entire vertical height of the gate separation structure and a first side surface and a second side surface, wherein an end surface of the first final gate structure contacts the first side surface and an end surface of the second final gate structure contacts the second side surface.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: December 29, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chanro Park, Ruilong Xie, Hui Zang, Laertis Economikos, Andre LaBonte
  • Patent number: 10790363
    Abstract: The disclosure relates to methods of forming integrated circuit (IC) structures with a metal cap on a cobalt layer for source and drain regions of a transistor. An integrated circuit (IC) structure according to the disclosure may include: a semiconductor fin on a substrate; a gate structure over the substrate, the gate structure having a first portion extending transversely across the semiconductor fin; an insulator cap positioned on the gate structure above the semiconductor fin; a cobalt (Co) layer on the semiconductor fin adjacent to the gate structure, wherein an upper surface of the Co layer is below an upper surface of the gate structure; and a metal cap on the Co layer.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: September 29, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Laertis Economikos, Kevin J. Ryan, Ruilong Xie, Hui Zang
  • Patent number: 10741656
    Abstract: This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor substrate having a first fin and a second fin spaced from the first fin; a first source/drain region in the first fin, the first source/drain region encompassing a top surface and two opposing lateral sides of the first fin; a second source/drain region in the second fin, the second source/drain encompassing a top surface and two opposing lateral sides of the second fin; and a metal contact extending over the first source/drain region and the second source/drain region and surrounding the top surface and at least a portion of the two opposing lateral sides of each of the first and the second source/drain regions.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: August 11, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Ruilong Xie, Shesh M. Pandey, Laertis Economikos
  • Patent number: 10741451
    Abstract: Processes form integrated circuit apparatuses that include parallel fins, wherein the fins are patterned in a first direction. Parallel gate structures intersect the fins in a second direction perpendicular to the first direction, wherein the gate structures have a lower portion adjacent to the fins and an upper portion distal to the fins. Source/drain structures are positioned on the fins between the gate structures. Source/drain contacts are positioned on the source/drain structures and multiple insulator layers are positioned between the gate structures and the source/drain contacts. Additional upper sidewall spacers are positioned between the upper portion of the gate structures and the multiple insulator layers.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: August 11, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Laertis Economikos, Shesh Mani Pandey, Chanro Park, Ruilong Xie
  • Patent number: 10727136
    Abstract: Methods of forming cross-coupling contacts for field-effect transistors and structures for field effect-transistors that include cross-coupling contacts. A dielectric cap is formed over a gate structure and a sidewall spacer adjacent to a sidewall of the gate structure. A portion of the dielectric cap is removed from over the sidewall spacer and the gate structure to expose a first portion of the gate electrode of the gate structure at a top surface of the gate structure. The sidewall spacer is then recessed relative to the gate structure to expose a portion of the gate dielectric layer at the sidewall of the gate structure, which is removed to expose a second portion of the gate electrode of the gate structure. A cross-coupling contact is formed that connects the first and second portions of the gate electrode of the gate structure with an epitaxial semiconductor layer adjacent to the sidewall spacer.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: July 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Ruilong Xie, Chanro Park, Laertis Economikos
  • Publication number: 20200227404
    Abstract: An integrated circuit (IC) includes an active area including at least one active fin-type field effect transistor (FinFET), and a trench isolation adjacent to the active area. At least one inactive gate is positioned over the trench isolation. A vertically extending resistor body is positioned adjacent the at least one inactive gate over the trench isolation. A lower end of the resistor is below an upper surface of the trench isolation. The resistor reduces interconnect layer thickness to improve yield, and significantly reduces resistor footprint to enable scaling.
    Type: Application
    Filed: January 10, 2019
    Publication date: July 16, 2020
    Inventors: Hui Zang, Guowei Xu, Jiehui Shu, Ruilong Xie, Yurong Wen, Garo J. Derderian, Shesh M. Pandey, Laertis Economikos
  • Patent number: 10707206
    Abstract: A method of forming a gate cut isolation, a related structure and IC are disclosed. The method forms a dummy gate material mandrel having a sidewall positioned between and spaced from a first active region covered by the mandrel and a second active region not covered by the mandrel. A gate cut dielectric layer is formed against the sidewall of the mandrel, and may be trimmed. A dummy gate material may deposited to encase the remaining gate cut dielectric layer. Subsequent dummy gate formation and replacement metal gate processing forms a gate conductor with the gate cut isolation electrically isolating respective first and second portions of the gate conductor. The method creates a very thin, slightly non-vertical gate cut isolation, and eliminates the need to define a gate cut critical dimension or fill a small gate cut opening.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: July 7, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Laertis Economikos, Ruilong Xie
  • Patent number: 10699957
    Abstract: Methods of forming a structure that includes field-effect transistor and structures that include a field effect-transistor. A dielectric cap is formed over a gate structure of a field-effect transistor, and an opening is patterned that extends fully through the dielectric cap to divide the dielectric cap into a first section and a second section spaced across the opening from the first surface. First and second dielectric spacers are respectively selectively deposited on respective first and second surfaces of the first and second sections of the dielectric cap to shorten the opening. A portion of the gate structure exposed through the opening between the first and second dielectric spacers is etched to form a cut that divides the gate electrode into first and second sections disconnected by the cut. A dielectric material is deposited in the opening and in the cut to form a dielectric pillar.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: June 30, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Ruilong Xie, Jiehui Shu, Chanro Park, Laertis Economikos
  • Publication number: 20200185509
    Abstract: At least one method, apparatus and system disclosed herein involves adjusting for a misalignment of a gate cut region with respect to semiconductor processing. A plurality of fins are formed on a semiconductor substrate. A gate region is formed over a portion of the fins. The gate region comprises a first dummy gate and a second dummy gate. A gate cut region is formed over the first dummy gate. A conformal fill material is deposited into the gate cut region. At least one subsequent processing step is performed.
    Type: Application
    Filed: December 30, 2019
    Publication date: June 11, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Laertis Economikos, Ruilong Xie
  • Publication number: 20200168509
    Abstract: Methods of forming a structure that includes field-effect transistor and structures that include a field effect-transistor. A dielectric cap is formed over a gate structure of a field-effect transistor, and an opening is patterned that extends fully through the dielectric cap to divide the dielectric cap into a first section and a second section spaced across the opening from the first surface. First and second dielectric spacers are respectively selectively deposited on respective first and second surfaces of the first and second sections of the dielectric cap to shorten the opening. A portion of the gate structure exposed through the opening between the first and second dielectric spacers is etched to form a cut that divides the gate electrode into first and second sections disconnected by the cut. A dielectric material is deposited in the opening and in the cut to form a dielectric pillar.
    Type: Application
    Filed: November 27, 2018
    Publication date: May 28, 2020
    Inventors: Hui Zang, Ruilong Xie, Jiehui Shu, Chanro Park, Laertis Economikos
  • Publication number: 20200161296
    Abstract: A method of forming a gate cut isolation, a related structure and IC are disclosed. The method forms a dummy gate material mandrel having a sidewall positioned between and spaced from a first active region covered by the mandrel and a second active region not covered by the mandrel. A gate cut dielectric layer is formed against the sidewall of the mandrel, and may be trimmed. A dummy gate material may deposited to encase the remaining gate cut dielectric layer. Subsequent dummy gate formation and replacement metal gate processing forms a gate conductor with the gate cut isolation electrically isolating respective first and second portions of the gate conductor. The method creates a very thin, slightly non-vertical gate cut isolation, and eliminates the need to define a gate cut critical dimension or fill a small gate cut opening.
    Type: Application
    Filed: November 19, 2018
    Publication date: May 21, 2020
    Inventors: Hui Zang, Laertis Economikos, Ruilong Xie
  • Publication number: 20200152509
    Abstract: A semiconductor device includes one or more fins extending from a substrate, the one or more fins having source/drain epitaxial grown material (S/D epitaxy) thereon that merges one or more fins, a gate formed over the one or more fins, the gate including high k metal gate disposed between gate spacers and a metal liner over the S/D epitaxy and sides of the gate spacers. The gate includes a self-aligned contact cap over the HKMG and the metal liner.
    Type: Application
    Filed: November 8, 2018
    Publication date: May 14, 2020
    Inventors: Andrew Greene, Ruilong Xie, Laertis Economikos, Veeraraghavan S. Basker, Chanro Park, Hui Zang
  • Publication number: 20200152518
    Abstract: Methods of forming cross-coupling contacts for field-effect transistors and structures for field effect-transistors that include cross-coupling contacts. A dielectric cap is formed over a gate structure and a sidewall spacer adjacent to a sidewall of the gate structure. A portion of the dielectric cap is removed from over the sidewall spacer and the gate structure to expose a first portion of the gate electrode of the gate structure at a top surface of the gate structure. The sidewall spacer is then recessed relative to the gate structure to expose a portion of the gate dielectric layer at the sidewall of the gate structure, which is removed to expose a second portion of the gate electrode of the gate structure. A cross-coupling contact is formed that connects the first and second portions of the gate electrode of the gate structure with an epitaxial semiconductor layer adjacent to the sidewall spacer.
    Type: Application
    Filed: November 9, 2018
    Publication date: May 14, 2020
    Inventors: Hui Zang, Ruilong Xie, Chanro Park, Laertis Economikos
  • Publication number: 20200135473
    Abstract: One integrated circuit product disclosed herein includes a first final gate structure for a first transistor device, a second final gate structure for a second transistor device, wherein the first and second transistor devices have a gate width that extends in a gate width direction and a gate length that extends in a gate length direction, and a gate separation structure positioned between the first and second final gate structures, the gate separation structure comprising at least one insulating material. The gate separation structure further has a substantially uniform width in the gate width direction for substantially an entire vertical height of the gate separation structure and a first side surface and a second side surface, wherein an end surface of the first final gate structure contacts the first side surface and an end surface of the second final gate structure contacts the second side surface.
    Type: Application
    Filed: November 11, 2019
    Publication date: April 30, 2020
    Inventors: Chanro Park, Ruilong Xie, Hui Zang, Laertis Economikos, Andre LaBonte
  • Publication number: 20200111713
    Abstract: Processes form integrated circuit apparatuses that include parallel fins, wherein the fins are patterned in a first direction. Parallel gate structures intersect the fins in a second direction perpendicular to the first direction, wherein the gate structures have a lower portion adjacent to the fins and an upper portion distal to the fins. Source/drain structures are positioned on the fins between the gate structures. Source/drain contacts are positioned on the source/drain structures and multiple insulator layers are positioned between the gate structures and the source/drain contacts. Additional upper sidewall spacers are positioned between the upper portion of the gate structures and the multiple insulator layers.
    Type: Application
    Filed: October 3, 2018
    Publication date: April 9, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Laertis Economikos, Shesh Mani Pandey, Chanro Park, Ruilong Xie
  • Publication number: 20200091143
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate cut structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and drain regions and sidewall spacers comprised of different dielectric materials; and contacts connecting to the source and drain regions and isolated from the gate structures by the different dielectric materials.
    Type: Application
    Filed: September 18, 2018
    Publication date: March 19, 2020
    Inventors: Hui ZANG, Ruilong XIE, Laertis ECONOMIKOS
  • Publication number: 20200083363
    Abstract: A device including oxide spacer in a contact over active gates (COAG) and method of production thereof. Embodiments include first gate structures over a fin of a substrate and second gate structures, each over an outer portion of the fin and a shallow trench isolation (STI) layer adjacent to the fin; a first raised source/drain (RSD) in a portion of the fin between the first gate structures and a second RSD in the portion of the fin between the first and second gate structures; a metal liner over the first and second RSD and on sidewall portions of the first and second gate structures; a metal layer over the metal liner; and an interlayer dielectric (ILD) over the metal liner and portions of the first and second gate structures.
    Type: Application
    Filed: September 10, 2018
    Publication date: March 12, 2020
    Inventors: Hui ZANG, Laertis ECONOMIKOS, Jiehui SHU, Ruilong XIE