Abstract: A method of forming transistors is provided. The method includes forming a plurality of transistor structures to have a plurality of dummy gates on a substrate. Each dummy gate is surrounded by sidewall spacers of a height, which is less than the dummy gate and is different for different transistor structures resulting in divots of different depths above the sidewall spacers. The method then deposits a conformal dielectric layer on top of the dummy gates and inside the divots of the plurality of transistor structures with the conformal dielectric layer having a thickness of at least half of a width of the divots, removes only a portion of the conformal dielectric layer that is on top of the dummy gates to expose the dummy gates; and replaces the dummy gates with a plurality of high-k metal gates.

Abstract: Cleaning solutions and processes for cleaning semiconductor devices or semiconductor tooling during manufacture thereof generally include contacting the semiconductor devices or semiconductor tooling with an acidic aqueous cleaning solution free of a fluorine containing compound, the acidic aqueous cleaning solution including at least one antioxidant and at least one non-oxidizing acid.

Abstract: A chemical mechanical polishing (CMP) system includes a rotating polishing table including a platen providing at least two pressure zones having different pressures; a sub-pad positioned on the platen, the sub-pad including a plurality of openings allowing for transmission of the different pressures therethrough; a fixed abrasive pad positioned on the sub-pad; and a pressure-creating system sealingly coupled to the platen for creating a different pressure in the at least two pressure zones, wherein the different pressures create topography on the fixed abrasive pad. A sub-pad and related method are also provided.

Abstract: A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.

Abstract: A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error.

Abstract: Methods of fabricating replacement metal gate transistors using bi-layer a hardmask are disclosed. By utilizing a bi-layer hardmask comprised of a first layer of nitride, followed by a second layer of oxide, the topography issues caused by transition regions of gates are mitigated, which simplifies downstream processing steps and improves yield.

Abstract: Methods of fabricating replacement metal gate transistors using bi-layer a hardmask are disclosed. By utilizing a bi-layer hardmask comprised of a first layer of nitride, followed by a second layer of oxide, the topography issues caused by transition regions of gates are mitigated, which simplifies downstream processing steps and improves yield.

Abstract: Cleaning solutions and processes for cleaning semiconductor devices or semiconductor tooling during manufacture thereof generally include contacting the semiconductor devices or semiconductor tooling with an acidic aqueous cleaning solution free of a fluorine containing compound, the acidic aqueous cleaning solution including at least one antioxidant and at least one non-oxidizing acid.

Abstract: Pitch-dependent dishing and erosion following CMP treatment of copper features is quantitatively assessed by atomic force microscopy (AFM) and transmission electron microscopy (TEM). A new sequence of processing steps presented herein is used to prevent dishing and to reduce significantly the local pitch- and pattern density-induced CMP non-uniformity for copper metal lines having widths and spacing in the range of about 32-128 nm. The new process includes a partial copper deposition step followed by deposition of a silicon carbide/nitride (SiCxNy) blocking layer. A multi-step CMP process planarizes areas of the resulting irregular surface that have narrow features, while the blocking layer protects areas that have wide features.

Abstract: A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error.

Abstract: A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error.

Abstract: A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error.

Abstract: The present disclosure is directed to fluid filtering systems and methods for use during semiconductor processing. One or more embodiments are directed to fluid filtering systems and methods for filtering ions and particles from a fluid as the fluid is being provided to a semiconductor wafer processing tool, such as to a semiconductor wafer cleaning tool.

Abstract: A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.

Abstract: A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.

Abstract: A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced.

Abstract: A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error.

Abstract: A polishing process in a semiconductor device fabrication process employs a polishing composition in which a gaseous phase is created within the polishing composition. During a polishing process, the gaseous phase dynamically responds to changes in the surface profile of the material undergoing removal by chemical and abrasive action during polishing. The inert gas bubble density dynamically increases in proximity to surface region of the substrate being polished that are prone to dishing and erosion. The increased inert gas bubble density operates to reduce the polish removal rate relative to other regions of the substrate. The dynamic action of the gaseous phase within the polishing composition functions to selectively reduce the localized polish removal rate such that a uniformly smooth and flat polished surface is obtained that is independent of the influence of pattern density during the polishing process.

Abstract: Methods, apparatus and computer program products provide a fast and accurate model for simulating the effects of chemical mechanical polishing (CMP) steps during fabrication of an integrated circuit by generating a design of an integrated circuit; while generating the design of the integrated circuit, using a simplified model to predict at least one physical characteristic of the integrated circuit which results from a CMP processing step to be used during manufacture of the integrated circuit, wherein the simplified model is derived from simulations performed prior to the design generation activities using a comprehensive simulation program used to model the physical characteristic; predicting performance of the integrated circuit using the predicted physical characteristic; and adjusting the design of the integrated circuit in dependence on the performance prediction.

Abstract: A chemical mechanical polishing (CMP) system includes a rotating polishing table including a platen providing at least two pressure zones having different pressures; a sub-pad positioned on the platen, the sub-pad including a plurality of openings allowing for transmission of the different pressures therethrough; a fixed abrasive pad positioned on the sub-pad; and a pressure-creating system sealingly coupled to the platen for creating a different pressure in the at least two pressure zones, wherein the different pressures create topography on the fixed abrasive pad. A sub-pad and related method are also provided.