Abstract: Processes form integrated circuit apparatuses that include parallel fins, wherein the fins are patterned in a first direction. Parallel gate structures intersect the fins in a second direction perpendicular to the first direction, wherein the gate structures have a lower portion adjacent to the fins and an upper portion distal to the fins. Source/drain structures are positioned on the fins between the gate structures. Source/drain contacts are positioned on the source/drain structures and multiple insulator layers are positioned between the gate structures and the source/drain contacts. Additional upper sidewall spacers are positioned between the upper portion of the gate structures and the multiple insulator layers.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate cut structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and drain regions and sidewall spacers comprised of different dielectric materials; and contacts connecting to the source and drain regions and isolated from the gate structures by the different dielectric materials.

Abstract: A device including oxide spacer in a contact over active gates (COAG) and method of production thereof. Embodiments include first gate structures over a fin of a substrate and second gate structures, each over an outer portion of the fin and a shallow trench isolation (STI) layer adjacent to the fin; a first raised source/drain (RSD) in a portion of the fin between the first gate structures and a second RSD in the portion of the fin between the first and second gate structures; a metal liner over the first and second RSD and on sidewall portions of the first and second gate structures; a metal layer over the metal liner; and an interlayer dielectric (ILD) over the metal liner and portions of the first and second gate structures.

Abstract: In conjunction with a replacement metal gate (RMG) process for forming a fin field effect transistor (FinFET), gate isolation methods and associated structures leverage the formation of distinct narrow and wide gate cut regions in a sacrificial gate. The formation of a narrow gate cut between closely-spaced fins can decrease the extent of etch damage to interlayer dielectric layers located adjacent to the narrow gate cut by delaying the deposition of such dielectric layers until after formation of the narrow gate cut opening. The methods and resulting structures also decrease the propensity for short circuits between later-formed, adjacent gates.

Abstract: This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor substrate having a first fin and a second fin spaced from the first fin; a first source/drain region in the first fin, the first source/drain region encompassing a top surface and two opposing lateral sides of the first fin; a second source/drain region in the second fin, the second source/drain encompassing a top surface and two opposing lateral sides of the second fin; and a metal contact extending over the first source/drain region and the second source/drain region and surrounding the top surface and at least a portion of the two opposing lateral sides of each of the first and the second source/drain regions.

Abstract: A methodology for forming a fin field effect transistor (FinFET) includes the co-integration of various isolation structures, including gate cut and shallow diffusion break isolation structures that are formed with common masking and etching steps. Following an additional patterning step to provide segmentation for source/drain conductive contacts, a single deposition step is used to form an isolation dielectric layer within each of gate cut openings, shallow diffusion break openings and cavities over shallow trench isolation between device active areas.

Abstract: A transistor device disclosed herein includes, among other things, a gate electrode positioned above a semiconductor material region, a sidewall spacer positioned adjacent the gate electrode, a gate insulation layer having a first portion positioned between the gate electrode and the semiconductor material region and a second portion positioned between a lower portion of the sidewall spacer and the gate electrode along a portion of a sidewall of the gate electrode, an air gap cavity located between the sidewall spacer and the gate electrode and above the second portion of the gate insulation layer, and a gate cap layer positioned above the gate electrode, wherein the gate cap layer seals an upper end of the air gap cavity so as to define an air gap positioned adjacent the gate electrode.

Abstract: A device including oxide spacer in a contact over active gates (COAG) and method of production thereof. Embodiments include first gate structures over a fin of a substrate and second gate structures, each over an outer portion of the fin and a shallow trench isolation (STI) layer adjacent to the fin; a first raised source/drain (RSD) in a portion of the fin between the first gate structures and a second RSD in the portion of the fin between the first and second gate structures; a metal liner over the first and second RSD and on sidewall portions of the first and second gate structures; a metal layer over the metal liner; and an interlayer dielectric (ILD) over the metal liner and portions of the first and second gate structures.

Abstract: A method that includes forming a conductive source/drain structure that is conductively coupled to source/drain regions of first and second transistor devices, selectively forming a conductive source/drain metallization cap structure on and in contact with an upper surface of the conductive source/drain structure, forming a patterned etch mask that exposes a portion of the gate cap and a portion of the conductive source/drain metallization cap structure, and performing at least one etching process to remove the exposed portion of the gate cap and thereafter an exposed portion of the final gate structure so as to form a gate cut opening, wherein the conductive source/drain metallization cap structure protects the underlying conductive source/drain structure during the at least one etching process.

Abstract: At least one method, apparatus, and system providing semiconductor devices comprising a first gate having a first width and comprising a first work function metal (WFM); a first liner disposed over the first WFM; a first gate metal having a first height; and a first pinch-off spacer over the first WFM, the first liner, and the first gate metal to above the first height; and a second gate having a second width greater than the first width, and comprising a second WFM; a second liner disposed over the second WFM; a second gate metal having substantially the first height; and a first conformal spacer over the second WFM and the second liner.

Abstract: The disclosure relates to methods of forming integrated circuit (IC) structures with a metal cap on a cobalt layer for source and drain regions of a transistor. An integrated circuit (IC) structure according to the disclosure may include: a semiconductor fin on a substrate; a gate structure over the substrate, the gate structure having a first portion extending transversely across the semiconductor fin; an insulator cap positioned on the gate structure above the semiconductor fin; a cobalt (Co) layer on the semiconductor fin adjacent to the gate structure, wherein an upper surface of the Co layer is below an upper surface of the gate structure; and a metal cap on the Co layer.

Abstract: At least one method, apparatus and system disclosed herein involves adjusting for a misalignment of a gate cut region with respect to semiconductor processing. A plurality of fins are formed on a semiconductor substrate. A gate region is formed over a portion of the fins. The gate region comprises a first dummy gate and a second dummy gate. A gate cut region is formed over the first dummy gate. A conformal fill material is deposited into the gate cut region. At least one subsequent processing step is performed.

Abstract: Disclosed is a method of forming an integrated circuit (IC) and the resulting structure. The method includes forming a transistor with a sacrificial gate on a channel region, a gate sidewall spacer on the sacrificial gate, and sacrificial plugs on the source/drain regions. The sacrificial gate is replaced with a gate, a gate cap on the gate, and a sacrificial cap on the gate cap and the gate sidewall spacer (which was recessed). Thus, top surfaces of the gate cap and gate sidewall spacer are at a lower level than the top surfaces of the sacrificial plugs and, when the sacrificial plugs are replaced with metal plugs, the gate cap is protected. In the resulting structure, the gate cap has a desired thickness and the top surface of the gate cap is at a lower level than the top surfaces of the metal plugs to reduce the risk of shorts.

Abstract: Disclosed is a method of forming an integrated circuit (IC) and the resulting structure. The method includes forming a transistor with a sacrificial gate on a channel region, a gate sidewall spacer on the sacrificial gate, and sacrificial plugs on the source/drain regions. The sacrificial gate is replaced with a gate, a gate cap on the gate, and a sacrificial cap on the gate cap and the gate sidewall spacer (which was recessed). Thus, top surfaces of the gate cap and gate sidewall spacer are at a lower level than the top surfaces of the sacrificial plugs and, when the sacrificial plugs are replaced with metal plugs, the gate cap is protected. In the resulting structure, the gate cap has a desired thickness and the top surface of the gate cap is at a lower level than the top surfaces of the metal plugs to reduce the risk of shorts.

Abstract: A methodology for forming a fin field effect transistor (FinFET) includes the co-integration of various isolation structures, including gate cut and shallow diffusion break isolation structures that are formed with common masking and etching steps. Following an additional patterning step to provide segmentation for source/drain conductive contacts, a single deposition step is used to form an isolation dielectric layer within each of gate cut openings, shallow diffusion break openings and cavities over shallow trench isolation between device active areas.

Abstract: A device including RM below the top surface of an HKMG structure, and method of production thereof. Embodiments include first and second HKMG structures over a portion of the substrate and on opposite sides of the STI region, the first and second HKMG structures having a top surface; and a RM over the STI region and between the first and second HKMG structures, wherein the RM is below the top surface of the first and second HKMG structures.

Abstract: Parallel fins are formed (in a first orientation), and source/drain structures are formed in or on the fins, where channel regions of the fins are between the source/drain structures. Parallel gate structures are formed to intersect the fins (in a second orientation perpendicular to the first orientation), source/drain contacts are formed on source/drain structures that are on opposite sides of the gate structures, and caps are formed on the source/drain contacts. After forming the caps, a gate cut structure is formed interrupting the portion of the gate structure that extends between adjacent fins. The upper portion of the gate cut structure includes extensions, where a first extension extends into one of the caps on a first side of the gate cut structure, and a second extension extends into the inter-gate insulator on a second side of the gate cut structure.

Abstract: A method of forming transistor devices with an air gap in the replacement gate structure is disclosed including forming a placeholder gate structure above a semiconductor material region, forming a sidewall spacer adjacent the placeholder gate structure, removing the placeholder gate structure to define a gate cavity bounded by the sidewall spacer, forming a gate insulation layer in the gate cavity, the gate insulation layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, forming a gate electrode in the gate cavity above the gate insulation layer, removing at least a portion of the second portion of the gate insulation layer to define an air gap cavity adjacent the gate electrode, and forming a first gate cap layer above the gate electrode, wherein the first gate cap layer seals an upper end of the air gap cavity.

Abstract: A device is formed including fins formed above a substrate, an isolation structure between the fins, a plurality of structures defining gate cavities, and a first dielectric material positioned between the structures. A patterning layer above the first dielectric material and in the gate cavities has a first opening positioned above a first gate cavity exposing a portion of the isolation structure and defining a first recess, a second opening above a second gate cavity exposing a first portion of the fins, and a third opening above a first portion of a source/drain region in the fins to expose the first dielectric material. Using the patterning layer, a second recess is formed in the substrate and a third recess is defined in the first dielectric material. A second dielectric material is formed in the recesses to define a gate cut structure, a diffusion break structure, and a contact cut structure.

Abstract: Parallel fins are formed (in a first orientation), and source/drain structures are formed in or on the fins, where channel regions of the fins are between the source/drain structures. Parallel gate structures are formed to intersect the fins (in a second orientation perpendicular to the first orientation), source/drain contacts are formed on source/drain structures that are on opposite sides of the gate structures, and caps are formed on the source/drain contacts. After forming the caps, a gate cut structure is formed interrupting the portion of the gate structure that extends between adjacent fins. The upper portion of the gate cut structure includes extensions, where a first extension extends into one of the caps on a first side of the gate cut structure, and a second extension extends into the inter-gate insulator on a second side of the gate cut structure.