Patents by Inventor Lain-Jong Li

Lain-Jong Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240030325
    Abstract: A transistor device having fin structures, source and drain terminals, channel layers and a gate structure is provided. The fin structures are disposed on a material layer. The fin structures are arranged in parallel and extending in a first direction. The source and drain terminals are disposed on the fin structures and the material layer and cover opposite ends of the fin structures. The channel layers are disposed respectively on the fin structures, and each channel layer extends between the source and drain terminals on the same fin structure. The gate structure is disposed on the channel layers and across the fin structures. The gate structure extends in a second direction perpendicular to the first direction. The materials of the channel layers include a transition metal and a chalcogenide, the source and drain terminals include a metallic material, and the channel layers are covalently bonded with the source and drain terminals.
    Type: Application
    Filed: October 3, 2023
    Publication date: January 25, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Lu, Chao-Ching Cheng, Tzu-Ang Chao, Lain-Jong Li
  • Publication number: 20230378334
    Abstract: A device includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, an isolation layer over the low-k dielectric layer, and a work function layer over the isolation layer. The work function layer is an n-type work function layer. The device further includes a low-dimensional semiconductor layer on a top surface and a sidewall of the work function layer, source/drain contacts contacting opposing end portions of the low-dimensional semiconductor layer, and a dielectric doping layer over and contacting a channel portion of the low-dimensional semiconductor layer. The dielectric doping layer includes a metal selected from aluminum and hafnium, and the channel portion of the low-dimensional semiconductor layer further comprises the metal.
    Type: Application
    Filed: August 3, 2023
    Publication date: November 23, 2023
    Inventors: Chun-Chieh Lu, Tzu Ang Chao, Chao-Ching Cheng, Lain-Jong Li
  • Patent number: 11824106
    Abstract: A transistor device having fin structures, source and drain terminals, channel layers and a gate structure is provided. The fin structures are disposed on a material layer. The fin structures are arranged in parallel and extending in a first direction. The source and drain terminals are disposed on the fin structures and the material layer and cover opposite ends of the fin structures. The channel layers are disposed respectively on the fin structures, and each channel layer extends between the source and drain terminals on the same fin structure. The gate structure is disposed on the channel layers and across the fin structures. The gate structure extends in a second direction perpendicular to the first direction. The materials of the channel layers include a transition metal and a chalcogenide, the source and drain terminals include a metallic material, and the channel layers are covalently bonded with the source and drain terminals.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: November 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Lu, Chao-Ching Cheng, Tzu-Ang Chao, Lain-Jong Li
  • Publication number: 20230369404
    Abstract: A semiconductor structure includes a semiconductor substrate, a plurality of stacked units, a conductive structure, a plurality of dielectrics, a first electrode strip, a second electrode strip, and a plurality of contact structures. The stacked units are stacked up over the semiconductor substrate, and comprises a first passivation layer, a second passivation layer and a channel layer sandwiched between the first passivation layer and the second passivation layer. The conductive structure is disposed on the semiconductor substrate and wrapping around the stacked units. The dielectrics are surrounding the stacked units and separating the stacked units from the conductive structure. The first electrode strip and the second electrode strip are located on two opposing sides of the conductive structure. The contact structures are connecting the channel layer of each of the stacked units to the first electrode strip and the second electrode strip.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Wei Shen, Tse-An Chen, Tung-Ying Lee, Lain-Jong Li
  • Publication number: 20230360913
    Abstract: A semiconductor device and method of manufacturing using carbon nanotubes are provided. In embodiments a stack of nanotubes are formed and then a non-destructive removal process is utilized to reduce the thickness of the stack of nanotubes. A device such as a transistor may then be formed from the reduced stack of nanotubes.
    Type: Application
    Filed: July 21, 2023
    Publication date: November 9, 2023
    Inventors: Tzu-Ang Chao, Gregory Michael Pitner, Tse-An Chen, Lain-Jong Li, Yu Chao Lin
  • Patent number: 11784225
    Abstract: A semiconductor structure includes a semiconductor substrate, a plurality of stacked units, a conductive structure, a plurality of dielectrics, a first electrode strip, a second electrode strip, and a plurality of contact structures. The stacked units are stacked up over the semiconductor substrate, and comprises a first passivation layer, a second passivation layer and a channel layer sandwiched between the first passivation layer and the second passivation layer. The conductive structure is disposed on the semiconductor substrate and wrapping around the stacked units. The dielectrics are surrounding the stacked units and separating the stacked units from the conductive structure. The first electrode strip and the second electrode strip are located on two opposing sides of the conductive structure. The contact structures are connecting the channel layer of each of the stacked units to the first electrode strip and the second electrode strip.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: October 10, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Wei Shen, Tse-An Chen, Tung-Ying Lee, Lain-Jong Li
  • Publication number: 20230307234
    Abstract: The present disclosure describes a method that includes forming a first two-dimensional (2D) layer on a first substrate and attaching a second 2D layer to a carrier film. The method also includes bonding the second 2D layer to the first 2D layer to form a heterostack including the first and second 2D layers. The method further includes separating the first 2D layer of the heterostack from the first substrate and attaching the heterostack to a second substrate. The method further includes removing the carrier film from the second 2D layer.
    Type: Application
    Filed: May 11, 2023
    Publication date: September 28, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tse-An CHEN, Lain-Jong LI
  • Patent number: 11749528
    Abstract: A semiconductor device and method of manufacturing using carbon nanotubes are provided. In embodiments a stack of nanotubes are formed and then a non-destructive removal process is utilized to reduce the thickness of the stack of nanotubes. A device such as a transistor may then be formed from the reduced stack of nanotubes.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tzu-Ang Chao, Gregory Michael Pitner, Tse-An Chen, Lain-Jong Li, Yu Chao Lin
  • Patent number: 11688605
    Abstract: The present disclosure describes a method that includes forming a first two-dimensional (2D) layer on a first substrate and attaching a second 2D layer to a carrier film. The method also includes bonding the second 2D layer to the first 2D layer to form a heterostack including the first and second 2D layers. The method further includes separating the first 2D layer of the heterostack from the first substrate and attaching the heterostack to a second substrate. The method further includes removing the carrier film from the second 2D layer.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: June 27, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tse-An Chen, Lain-Jong Li
  • Publication number: 20230075396
    Abstract: A semiconductor device includes channel region, first and second two-dimensional metallic contacts, a gate structure, and first and second metal contacts. The channel region includes a two-dimensional semiconductor material. The first two-dimensional metallic contact is disposed at a side of the channel region and includes a two-dimensional metallic material. The second two-dimensional metallic contact is disposed at an opposite side of the channel region and includes the two-dimensional metallic material. The gate structure is disposed on the channel region in between the first and second two-dimensional metallic contacts. The first metal contact is disposed at an opposite side of the first two-dimensional metallic contact with respect to the channel region. The second metal contact is disposed at an opposite side of the second two-dimensional metallic contact with respect to the channel region.
    Type: Application
    Filed: November 10, 2022
    Publication date: March 9, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Yang Li, Lain-Jong Li, Han Yeh, Wen-Hao Chang
  • Publication number: 20230062389
    Abstract: A semiconductor structure includes a semiconductor substrate, a plurality of stacked units, a conductive structure, a plurality of dielectrics, a first electrode strip, a second electrode strip, and a plurality of contact structures. The stacked units are stacked up over the semiconductor substrate, and comprises a first passivation layer, a second passivation layer and a channel layer sandwiched between the first passivation layer and the second passivation layer. The conductive structure is disposed on the semiconductor substrate and wrapping around the stacked units. The dielectrics are surrounding the stacked units and separating the stacked units from the conductive structure. The first electrode strip and the second electrode strip are located on two opposing sides of the conductive structure. The contact structures are connecting the channel layer of each of the stacked units to the first electrode strip and the second electrode strip.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Wei Shen, Tse-An Chen, Tung-Ying Lee, Lain-Jong Li
  • Patent number: 11581185
    Abstract: In a method of forming a two-dimensional material layer, a nucleation pattern is formed over a substrate, and a transition metal dichalcogenide (TMD) layer is formed such that the TMD layer laterally grows from the nucleation pattern. In one or more of the foregoing and following embodiments, the TMD layer is single crystalline.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: February 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Yang Li, Lain-Jong Li, Chih-Piao Chuu
  • Patent number: 11538682
    Abstract: A method for growing a transition metal dichalcogenide layer involves arranging a substrate having a first transition metal contained pad is arranged in a chemical vapor deposition chamber. A chalcogen contained precursor is arranged upstream of the substrate in the chemical vapor deposition chamber. The chemical vapor deposition chamber is heated for a period of time during which a transition metal dichalcogenides layer, containing transition metal from the first transition metal contained pad and chalcogen from the chalcogen contained precursor, is formed in an area adjacent to the first transition metal contained pad.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: December 27, 2022
    Assignee: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Ming-Hui Chiu, Hao-Ling Tang, Lain-Jong Li
  • Patent number: 11527659
    Abstract: A semiconductor device includes channel region, first and second two-dimensional metallic contacts, a gate structure, and first and second metal contacts. The channel region includes a two-dimensional semiconductor material. The first two-dimensional metallic contact is disposed at a side of the channel region and includes a two-dimensional metallic material. The second two-dimensional metallic contact is disposed at an opposite side of the channel region and includes the two-dimensional metallic material. The gate structure is disposed on the channel region in between the first and second two-dimensional metallic contacts. The first metal contact is disposed at an opposite side of the first two-dimensional metallic contact with respect to the channel region. The second metal contact is disposed at an opposite side of the second two-dimensional metallic contact with respect to the channel region.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: December 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Yang Li, Lain-Jong Li, Han Yeh, Wen-Hao Chang
  • Publication number: 20220367207
    Abstract: A method of fabricating a semiconductor device includes applying a plasma to a portion of a metal dichalcogenide film. The metal dichalcogenide film includes a first metal and a chalcogen selected from the group consisting of S, Se, Te, and combinations thereof. A metal layer including a second metal is formed over the portion of the metal dichalcogenide film after applying the plasma.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 17, 2022
    Inventors: Chih-Piao CHUU, Ming-Yang LI, Lain-Jong LI
  • Publication number: 20220359737
    Abstract: A method includes: forming a dielectric fin protruding above a substrate; forming a channel layer over an upper surface of the dielectric fin and along first sidewalls of the dielectric fin, the channel layer including a low dimensional material; forming a gate structure over the channel layer; forming metal source/drain regions on opposing sides of the gate structure; forming a channel enhancement layer over the channel layer; and forming a passivation layer over the gate structure, the metal source/drain regions, and the channel enhancement layer.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Inventors: Yi-Tse Hung, Chao-Ching Cheng, Tse-An Chen, Hung-Li Chiang, Tzu-Chiang Chen, Lain-Jong Li
  • Publication number: 20220352312
    Abstract: A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 3, 2022
    Inventors: Chao-Ching Cheng, Tzu-Ang Chao, Chun-Chieh Lu, Hung-Li Chiang, Tzu-Chiang Chen, Lain-Jong Li
  • Patent number: 11476356
    Abstract: A method includes: forming a dielectric fin protruding above a substrate; forming a channel layer over an upper surface of the dielectric fin and along first sidewalls of the dielectric fin, the channel layer including a low dimensional material; forming a gate structure over the channel layer; forming metal source/drain regions on opposing sides of the gate structure; forming a channel enhancement layer over the channel layer; and forming a passivation layer over the gate structure, the metal source/drain regions, and the channel enhancement layer.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: October 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Tse Hung, Chao-Ching Cheng, Tse-An Chen, Hung-Li Chiang, Tzu-Chiang Chen, Lain-Jong Li
  • Publication number: 20220285612
    Abstract: An array of rail structures is formed over a substrate. Each rail structure includes at least one bit line. Dielectric isolation structures straddling the array of rail structures are formed. Line trenches are provided between neighboring pairs of the dielectric isolation structures. A layer stack of a resistive memory material layer and a selector material layer is formed within each of the line trenches. A word line is formed on each of the layer stacks within unfilled volumes of the line trenches. The word lines or at least a subset of the bit lines includes a carbon-based conductive material containing hybridized carbon atoms in a hexagonal arrangement to provide a low resistivity conductive structure. An array of resistive memory elements is formed over the substrate. A plurality of arrays of resistive memory elements may be formed at different levels over the substrate.
    Type: Application
    Filed: May 23, 2022
    Publication date: September 8, 2022
    Inventors: Hung-Li Chiang, Chao-Ching Cheng, Tzu-Chiang Chen, Lain-Jong Li
  • Patent number: 11430666
    Abstract: A method of fabricating a semiconductor device includes applying a plasma to a portion of a metal dichalcogenide film. The metal dichalcogenide film includes a first metal and a chalcogen selected from the group consisting of S, Se, Te, and combinations thereof. A metal layer including a second metal is formed over the portion of the metal dichalcogenide film after applying the plasma.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: August 30, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Piao Chuu, Ming-Yang Li, Lain-Jong Li