Abstract: A method for forming at least one barrierless, embedded metal structure comprising the following steps. A structure having a patterned dielectric layer formed thereover with at least one opening exposing at least one respective portion of the structure. Respective metal structures are formed within each respective opening. The first dielectric layer is removed to expose the top and at least a portion of the side walls of the respective at least one metal structure. A dielectric barrier layer is formed over the structure and the exposed top of the respective metal structure. A second, conformal dielectric layer is formed over the dielectric barrier layer to complete the respective barrierless at least one metal structure embedded within the second, conformal dielectric layer. The dielectric barrier layer preventing diffusion of the metal comprising the respective at least one metal structure into the second, conformal dielectric layer.

Abstract: This invention provides a method to improve the adhesion between dielectric material layers at the interface thereof, during the manufacture of a semiconductor device. The first step is to form a SiC-based dielectric material layer over a substrate. The SiC-based dielectric material layer is treated by oxygen plasma. A second layer of dielectric material is formed over the SiC-based dielectric material layer.

Abstract: A method of adhering a silicate layer to dielectric layer comprising the following steps. A structure having an overlying dielectric layer formed thereover is provided. An adhesion promoter layer is formed upon the dielectric layer. The adhesion promoter layer including adhesion promotion molecules. The dielectric layer and the adhesion promoter layer are treated to a low-temperature treatment to bind at least some of the adhesion promotion molecules to the dielectric layer. A silicate layer is formed upon the low-temperature treated adhesion promoter layer. The silicate layer and the low-temperature treated adhesion promoter layer are treated to a high-temperature treatment to bind at least some of the adhesion promotion molecules to the silicate layer whereby the silicate layer is adhered to the dielectric layer.

Abstract: Within a damascene method for forming a patterned conductor layer having formed interposed between its patterns a patterned dielectric layer formed of a comparatively low dielectric constant dielectric material method, there is employed a patterned capping layer formed upon the patterned dielectric layer. The patterned capping layer is formed employing a plasma enhanced chemical vapor deposition (PECVD) method in turn employing an organosilane carbon and silicon source material, a substrate temperature of from about 0 to about 200 degrees centigrade and a radio frequency power of from about 100 to about 1000 watts per square centimeter substrate area. The patterned capping layer provides for attenuated abrasive damage to the dielectric layer incident to the damascene method and is typically partially planarized incident to the damascene method.

Abstract: A new method of forming a composite etching stop layer is described. An etching stop layer is deposited on a substrate wherein the etching stop layer is selected from the group consisting of: silicon carbide, silicon nitride, SiCN, SiOC, and SiOCN. A TEOS oxide layer is deposited by plasma-enhanced chemical vapor deposition overlying the etching stop layer. The composite etching stop layer has improved moisture resistance, better etching selectivity, and lower dielectric constant than other etching stop layers.

Abstract: A process for depositing, through plasma enhanced chemical vapor deposition, inorganic films having low dielectric constant is disclosed. After deposition under low power for a few seconds the power is raised to high for a few seconds, deposition of the film continuing to alternate between low and high power modes until the total desired thickness is reached. Additionally, for the deposition of materials such as black diamond, oxygen is added to the plasma during the high power phase (and removed during the low power phase). We have found that films deposited in this way have low flat band voltages, close to zero, and are, in general, more robust than films deposited according to prior art methods. In particular, these films are free of the cracking problems often encountered during chemical mechanical polishing of films of this type during the formation of damascene structures.

Abstract: A method for forming at least one barrierless, embedded metal structure comprising the following steps. A structure having a patterned dielectric layer formed thereover with at least one opening exposing at least one respective portion of the structure. Respective metal structures are formed within each respective opening. The first dielectric layer is removed to expose the top and at least a portion of the side walls of the respective at least one metal structure. A dielectric barrier layer is formed over the structure and the exposed top of the respective metal structure. A second, conformal dielectric layer is formed over the dielectric barrier layer to complete the respective barrierless at least one metal structure embedded within the second, conformal dielectric layer. The dielectric barrier layer preventing diffusion of the metal comprising the respective at least one metal structure into the second, conformal dielectric layer.

Abstract: A method for reducing electrical charge imbalances in a semiconductor process wafer including providing a semiconductor process wafer including a dielectric insulating layer; exposing the semiconductor process wafer to a semiconductor process whereby an electrical charge imbalance accumulates in charge imbalance portions of the dielectric insulating layer; and, treating the semiconductor process wafer with a controlled atmosphere of treatment gas including at least one of inert gas and hydrogen to reduce an accumulated charge imbalance in the charge imbalance portions.

Abstract: A method for forming a capping layer for improved adhesion with an underlying insulating layer in a multiple layer semiconductor device manufacturing process including providing a semiconductor wafer including a process surface comprising a dielectric insulating layer; and, providing a capping layer overlying the dielectric insulating layer according to a chemical vapor deposition CVD) process. The capping layer of the present invention has improved adhesion and a reduced dielectric constant with comparable current leakage compared to capping layers of the prior art.

Abstract: A new method of forming a composite etching stop layer is described. An etching stop layer is deposited on a substrate wherein the etching stop layer is selected from the group consisting of: silicon carbide, silicon nitride, SiCN, SiOC, and SiOCN. A TEOS oxide layer is deposited by plasma-enhanced chemical vapor deposition overlying the etching stop layer. The composite etching stop layer has improved moisture resistance, better etching selectivity, and lower dielectric constant than other etching stop layers.

Abstract: A method of adhering a silicate layer to dielectric layer comprising the following steps. A structure having an overlying dielectric layer formed thereover is provided. An adhesion promoter layer is formed upon the dielectric layer. The adhesion promoter layer including adhesion promotion molecules. The dielectric layer and the adhesion promoter layer are treated to a low-temperature treatment to bind at least some of the adhesion promotion molecules to the dielectric layer. A silicate layer is formed upon the low-temperature treated adhesion promoter layer. The silicate layer and the low-temperature treated adhesion promoter layer are treated to a high-temperature treatment to bind at least some of the adhesion promotion molecules to the silicate layer whereby the silicate layer is adhered to the dielectric layer.

Abstract: A method for reducing electrical charge imbalances in a semiconductor process wafer including providing a semiconductor process wafer including a dielectric insulating layer; exposing the semiconductor process wafer to a semiconductor process whereby an electrical charge imbalance accumulates in charge imbalance portions of the dielectric insulating layer; and, treating the semiconductor process wafer with a controlled atmosphere of treatment gas including at least one of inert gas and hydrogen to reduce an accumulated charge imbalance in the charge imbalance portions.

Abstract: A method for forming a capping layer for improved adhesion with an underlying insulating layer in a multiple layer semiconductor device manufacturing process including providing a semiconductor wafer including a process surface comprising a dielectric insulating layer; and, providing a capping layer overlying the dielectric insulating layer according to a chemical vapor deposition CVD) process.

Abstract: Within a damascene method for forming a patterned conductor layer having formed interposed between its patterns a patterned dielectric layer formed of a comparatively low dielectric constant dielectric material method, there is employed a patterned capping layer formed upon the patterned dielectric layer. The patterned capping layer is formed employing a plasma enhanced chemical vapor deposition (PECVD) method in turn employing an organosilane carbon and silicon source material, a substrate temperature of from about 0 to about 200 degrees centigrade and a radio frequency power of from about 100 to about 1000 watts per square centimeter substrate area. The patterned capping layer provides for attenuated abrasive damage to the dielectric layer incident to the damascene method and is typically partially planarized incident to the damascene method.

Abstract: In accordance with the objectives of the invention a new method is provided for improving adhesion strength that is deposited over the surface of a layer of copper. Conventional etch stop layers of for instance dichlorosilane (SiCl2H2) or SiOC have poor adhesion with an underlying layer of copper due to poor molecular binding between the interfacing layers. The surface of the deposited layer of copper can be provided with a special enhanced interface layer by using a method provided by the invention. That is pre-heat of the copper layer followed by a pre-cleaning treatment with ammonia (NH3) and N2, followed by forming an adhesive enhanced layer over the copper layer by treatment with N2 or O2 or N2 with alkyl-silane or alkyl silane.

Abstract: This invention provides a method to improve the adhesion between dielectric material layers at the interface thereof, during the manufacture of a semiconductor device. The first step is to form a SiC-based dielectric material layer over a substrate. The SiC-based dielectric material layer is treated by oxygen plasma. A second layer of dielectric material is formed over the SiC-based dielectric material layer.

Abstract: Within a method for forming a dielectric layer, there is first provided a substrate. There is then formed over the substrate a dielectric layer, wherein the dielectric layer is formed from a dielectric material comprising silicon, carbon and nitrogen. Preferably, a nitrogen content is graded within a thickness of the dielectric layer to provide an upper lying nitrogen rich contiguous surface layer of the dielectric layer and a lower lying nitrogen poor contiguous layer of the dielectric layer. The method contemplates a microelectronic fabrication having formed therein a dielectric layer formed in accord with the method. The method provides the resulting dielectric layer with a lower dielectric constant and enhanced adhesion properties as a substrate layer.

Abstract: Defects such as holes and bumps in the surface of a semiconductor wafer are detected by an optical inspection system that combines darkfield and brightfield illumination techniques. A single light stop, which forms part of the illumination system, includes a pair of openings configured to produce both a solid cone of light and a hollow of light which are simultaneously focused onto the wafer surface. The directly emanating light as well as the scattered light collected from the wafer surface produce a resultant image that is the product of darkfield and brightfield illumination. Modulation of the light beam and tilting of the light focused onto the wafer surface may be advantageously used to improved contrast and resolution of the viewed image.

Abstract: A layer of low k dielectric is formed on a substrate having a conducting electrode formed therein. A via hole is formed in the low k dielectric exposing the conducting electrode. A thin layer of amorphous silicon is deposited on the layer of low k dielectric and on the sidewalls and bottom of a via hole. A layer of resist is then formed and patterned with a trench pattern. A trench is etched in the layer of low k dielectric directly over the via hole using the patterned layer of resist. The patterned layer of resist is then stripped and the trench and via hole are filled with conducting material. The layer of amorphous silicon prevents amine radicals, NHx, which can be released from the low k dielectric, especially during the via hole etching, from interacting with the resist and forming resist scum resulting in via poisoning.

Abstract: Attenuated total reflectance (ATR)-Fourier transform infrared (FTIR) metal surface cleanliness monitoring is disclosed. A metal surface of a semiconductor die is impinged with an infrared (IR) beam, such as can be accomplished by using an ATR technique. The IR beam as reflected by the metal surface is measured. For instance, an interferogram of the reflected IR beam may be measured. A Fourier transform of the interferogram may also be performed, in accordance with an FTIR technique. To determine whether the metal surface is contaminated, the IR beam as reflected is compared to a reference sample. For example, the Fourier transform of the interferogram may be compared to the reference sample. If there is deviation by more than a threshold, the metal surface may be concluded as being contaminated.