Abstract: A method and apparatus for platform component interconnect testing is disclosed. In one embodiment, an integrated circuit comprises: a plurality of interface circuitries, wherein each interface circuitry comprises a driver with adjustable pullup and pulldown resistances and having a driver output to output a driver voltage to a pad during test mode, and a comparator having a first input coupled to the driver output and a second input coupled to a voltage reference, the comparator being operable to generate a comparator output in response to comparing the driver voltage with the voltage reference; and analysis circuitry coupled to receive the comparator output, the analysis circuitry operable, during the test mode, to detect existence of a fault associated with a signal path coupled to the pad for each interface circuitry.

Abstract: Techniques and mechanisms for providing on-chip link control functionality to facilitate emulation of a communication. In an embodiment, an integrated circuit (IC) chip includes a physical layer (PHY) which supports communication compatible with a high-speed serial interface standard. A link controller of the IC chip is coupled between the PHY and an interconnect architecture which variously couples a host and other resources of the IC chip to each other. A test controller of the IC chip signals a test mode to implement a loopback path of the link controller in lieu of one or more functional paths for communication with the PHY. In another embodiment, signal output by the loopback path emulate a communication from a resource other than the test controller.

Abstract: An electronic device, an electronic system, or a method may be used for testing an electronic device. The electronic device may include a virtual touch circuit. The virtual touch circuit may be configured to transmit testing data. The testing data may represent sensory input data. The electronic device may include a touch host controller. The touch host controller may be configured to process sensory data inputs. The sensory data inputs may include the testing data. The electronic device may include a validation circuit. The validation circuit may be configured to evaluate performance of the touch host controller. The validation circuit may evaluate the performance of the touch host controller by using the testing data that was processed by the touch host controller. The touch host controller, the virtual touch circuit, and the validation circuit may be included in a single die.

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing SoC coverage through virtual devices in PCIe and DMI controllers.

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing high speed serial controller testing.

Abstract: A system includes test control circuitry in parallel with power control circuitry. The power control circuitry enables a core processor and memory interface drivers responsive to a reset. The test control circuitry can enable the memory interface drivers separately from the core processor to enable testing of the connections to the memory devices. The test control circuitry is triggered separately from the other power control circuitry, and can be protected to allow only secured access for testing.

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing virtual device observation and debug network for high speed serial IOS.

Abstract: In one embodiment, a request may be received to load firmware on a microcontroller of a device. A firmware transfer may be initiated to load the firmware on the microcontroller. Data traffic may be monitored at one or more locations on a communication path associated with the firmware transfer. It may be determined whether the data traffic matches a digital fingerprint associated with the firmware.

Abstract: Techniques and mechanisms to modify packet information in support of on-chip test functionality. In an embodiment, an integrated circuit (IC) chip includes a protocol stack to receive and process packetized information—e.g., where the processing of at least one isochronous timestamp packet (ITP) includes circuitry of the protocol stack replacing non-deterministic data of the ITP with substitute information. A deterministic nature of the substitute information enables the subsequent generation of corresponding signature information which can be used in an evaluation of circuit performance. In another embodiment, the ITP packet is modified at a transaction layer of the protocol stack, and the signature information is determined with an accumulator circuit which is part of another layer of the protocol stack.

Abstract: Embodiments are generally directed to display controller testing through a high speed communications switch. An embodiment of an apparatus includes a display controller including a first test machine; a high speed switch coupled with the display controller; and one or more physical layer (PHY) logic elements including a first PHY with a second test machine, the first test machine and second test machine being replicas of each other at least in part. The first test machine and the second test machine are operable to synchronously lock with each other, the first test machine to generate a data sequence and transmit the data sequence to the second test machine, the second test machine to generate an expected data sequence and compare the expected data sequence to a received data sequence from the first test machine.

Abstract: An apparatus is provided which comprises: a power management circuitry; and a processing circuitry comprising a processing core, wherein the power management circuitry is to: compute first voltage and frequency parameters, and transmit the first voltage and frequency parameters to the processing circuitry for operation of the processing core, and wherein in response to a detection of a fault, the power management circuitry is to: access second voltage and frequency parameters from a memory, and transmit the accessed second voltage and frequency parameters to the processing circuitry for operation of the processing core.

Abstract: Embodiments are generally directed to maintaining IO block operation in electronic systems for board testing. An embodiment of a system includes a processor; a power management block for the system; a plurality of IO (input/output) blocks; a read only memory for storage of firmware for the processor. The system is to provide support for a board-level test of the system including testing of one or more IO blocks of the plurality of IO blocks; and the firmware includes elements to stall a reset sequence of the system including the system branching to a mode that maintains power to the one or more IO blocks.

Abstract: Embodiments are generally directed to a protocol aware testing engine for high speed link integrity testing. An embodiment of a processor includes a processing core for processing data; and a protocol aware testing engine, wherein the protocol aware testing engine includes a protocol aware packet generator to generate test packets in compliance with an IO protocol, and a packet aligning and checking unit to align test packets generated by the packet generator with returned test packets and to compare the generated test packets with the returned data packets.

Abstract: Embodiments are generally directed to board level leakage testing for a memory interface. An embodiment of an apparatus includes multiple logic cells for testing of a memory interface, each logic cell being connected to an interconnect for a respective memory element. Each logic cell includes a driver to drive a signal onto the interconnect with the respective memory element, an element to generate a value for the logic cell by comparing a signal with a reference voltage, a flip-flop to capture a cell value for the logic cell, and a drive control element to control the value driven on the interconnect by the driver. The apparatus further includes a processor to identify failure conditions based at least in part on testing using the logic cells.

Abstract: Embodiments are generally directed to phase lock loop bypass for board level testing of systems. An embodiment of system includes a power management block for the system; multiple IO (input/output) blocks; a phase lock loop (PLL) block for each of the IO blocks, each of the phase lock loop blocks being switchable between providing an output of a PLL clock signal or providing a replacement clock signal as clocking for the respective IO block; and a read only memory for storage of firmware. In some embodiments, the firmware includes elements to enable operation of the plurality of IO blocks utilizing replacement clocking.

Abstract: An electronic device, an electronic system, or a method may be used for testing an electronic device. The electronic device may include a virtual touch circuit. The virtual touch circuit may be configured to transmit testing data. The testing data may represent sensory input data. The electronic device may include a touch host controller. The touch host controller may be configured to process sensory data inputs. The sensory data inputs may include the testing data. The electronic device may include a validation circuit. The validation circuit may be configured to evaluate performance of the touch host controller. The validation circuit may evaluate the performance of the touch host controller by using the testing data that was processed by the touch host controller. The touch host controller, the virtual touch circuit, and the validation circuit may be included in a single die.

Abstract: Systems, methods, and apparatuses for implementing die recovery in Two-Level Memory (2LM) stacked die subsystems are described. A stacked semiconductor package includes a processor functional silicon die at a first layer of the stacked semiconductor package; one or more memory dies forming a corresponding one or more memory layers of the stacked semiconductor package; a plurality of Through Silicon Vias (TSV s) formed through the one or more memory dies; a plurality of physical memory interfaces electrically interfacing the one or more memory dies to the processor functional silicon die at the first layer through the memory layers via the plurality of TSVs; and a redundant physical memory interface formed by a redundant TSV traversing through the memory layers to the processor functional silicon die at the first layer through which to reroute a memory signal path from a defective physical memory interface at a defective TSV to a functional signal path traversing the redundant TSV.

Abstract: Embodiments include apparatuses, methods, and systems for testing that include a programmable tester coupled to a master-slave device network having a master device and at least one slave device. The programmable tester is to receive a configuration mode from a host to test a function of a selected device of the master device or the at least one slave device. The configuration mode is to indicate that the programmable tester is to be configured to operate in a slave mode or in a master mode. The programmable tester is further configured according to the configuration mode, to send test data to test the function of the selected device, determine a test result based on response data by the selected device to the test data, and indicate whether the selected device is in a faulty state with respect to the function. Other embodiments may also be described and claimed.

Abstract: Embodiments are generally directed to a mechanism to provide back-to-back testing of memory controller operation. An embodiment of an apparatus includes a test controller including a specialized self-testing mechanism for memory control testing, the memory control testing including testing with back-to-back transactions; and a memory controller, the memory controller including one or more transaction arbiters, one or more arbiter queues for memory transactions, an auto response mechanism to provide a response to a read transaction, and a switching mechanism to switch the memory control between a functional mode and an auto response mode. The test controller is to generate test transactions and transfer the test transactions to the memory controller. The memory controller is to block the one or more transaction arbiters, place the plurality of test transactions in the one or more arbiter queues, and to unblock the transaction arbiters upon an event.

Abstract: In one embodiment, an apparatus includes: an accelerator to execute instructions; an accelerator request decoder coupled to the accelerator to perform a first level decode of requests from the accelerator and direct the requests based on the first level decode, the accelerator request decoder including a memory map to identify a first address range associated with a local memory and a second address range associated with a system memory; and a non-coherent request router coupled to the accelerator request decoder to receive non-coherent requests from the accelerator request decoder and perform a second level decode of the non-coherent requests, the non-coherent request router to route first non-coherent requests to a sideband router of the first die and to direct second non-coherent requests to a computing die. Other embodiments are described and claimed.