Abstract: In one embodiment, a request may be received to load firmware from an external component to a microcontroller of a device. The external component may be authenticated, and the firmware may be loaded from the external component to the microcontroller using a firmware loading controller of the device, wherein the firmware is loaded using direct memory access without accessing system memory associated with the device.

Abstract: A method and apparatus for platform component interconnect testing is disclosed. In one embodiment, an integrated circuit comprises: a plurality of interface circuitries, wherein each interface circuitry comprises a driver with adjustable pullup and pulldown resistances and having a driver output to output a driver voltage to a pad during test mode, and a comparator having a first input coupled to the driver output and a second input coupled to a voltage reference, the comparator being operable to generate a comparator output in response to comparing the driver voltage with the voltage reference; and analysis circuitry coupled to receive the comparator output, the analysis circuitry operable, during the test mode, to detect existence of a fault associated with a signal path coupled to the pad for each interface circuitry.

Abstract: Stacked semiconductor packages and methods for performing bare die testing on a functional silicon die in a stacked semiconductor package are described. In an example, a stacked semiconductor package includes a functional silicon die, a test controller having signature accumulation logic embedded therein, and a fabric to route transactions between the test controller and any of a plurality of near memory controllers of the functional silicon die.

Abstract: One embodiment provides an apparatus. The apparatus includes a functional test controller. The functional test controller includes controller logic to receive communication protocol-specific data comprising a packet header from a tester; a protocol buffer to store the packet header; and a pseudorandom bit sequence (PRBS) generator to generate a PRBS. The controller logic is to combine the packet header and the PRBS into a packet and to provide the packet to an input/output (I/O) controller under test.

Abstract: A stacked semiconductor package comprising a functional silicon die having embedded thereupon a Wide Input/Output 2 (WIO2) interface, and two or more memory dies forming a corresponding two or more memory layers of the stacked semiconductor package. A plurality of Through Silicon Vias (TSVs) are formed through the two or more memory dies, wherein each of the plurality of TSVs traverse through the two or more memory layers to the functional silicon die via the WIO2 interface of the functional silicon die. A test port interface receives test signals from an external tester and routes the test signals through a steering logic communicably interfaced with the two or more memory dies. The steering logic shifts data into and out of the two or more memory dies through the plurality of TSVs.

Abstract: Embodiments are generally directed to a protocol aware testing engine for high speed link integrity testing. An embodiment of a processor includes a processing core for processing data; and a protocol aware testing engine, wherein the protocol aware testing engine includes a protocol aware packet generator to generate test packets in compliance with an IO protocol, and a packet aligning and checking unit to align test packets generated by the packet generator with returned test packets and to compare the generated test packets with the returned data packets.

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing die recovery in Two-Level Memory (2LM) stacked die subsystems.

Abstract: A stacked semiconductor package comprising a functional silicon die having embedded thereupon a Wide Input/Output 2 (WIO2) interface, and two or more memory dies forming a corresponding two or more memory layers of the stacked semiconductor package. A plurality of Through Silicon Vias (TSVs) are formed through the two or more memory dies, wherein each of the plurality of TSVs traverse through the two or more memory layers to the functional silicon die via the WIO2 interface of the functional silicon die. A test port interface receives test signals from an external tester and routes the test signals through a steering logic communicably interfaced with the two or more memory dies. The steering logic shifts data into and out of the two or more memory dies through the plurality of TSVs.

Abstract: Stacked semiconductor packages and methods for performing bare die testing on a functional silicon die in a stacked semiconductor package are described. In an example, a stacked semiconductor package includes a functional silicon die, a test controller having signature accumulation logic embedded therein, and a fabric to route transactions between the test controller and any of a plurality of near memory controllers of the functional silicon die.

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing testing of a far memory subsystem within Two-Level Memory (2LM) stacked die subsystems. For instance, there is in accordance with one embodiment a stacked semiconductor package which includes: a functional silicon die; a test controller having signature accumulation logic embedded therein; a fabric to route transactions between the test controller and a far memory controller of the functional silicon die; in which the far memory controller includes a physical memory interface having no physical memory attached; a Two Level Memory (2LM) controller having logic to modify received transactions to indicate a cache miss forcing all received transactions to be routed to the far memory controller via the fabric; and an auto response mechanism to observe the transactions on the fabric and route responses and completions issued in reply to the transactions back to an agent having initiated the transactions.

Abstract: Described is a signature accumulator with a first set of logic devices, a second set of logic devices, and a memory device. The first set of logic devices includes compaction logic that couples an N-bit input bus to a K-bit first intermediate bus. The second set of logic devices includes commutative arithmetic operation logic that couples both the K-bit first intermediate bus and a K-bit signature bus to a K-bit second intermediate bus. The memory storage device includes a storage element that couples the K-bit second intermediate bus to the K-bit signature bus. The K-bit signature bus is also coupled to a valid-data input signal path.

Abstract: Described is a host interface, a device interface, a downstream translation circuitry, an upstream translation circuitry, and a host line-state state machine. The host interface may comprise a host line-state output. The device interface may comprise a device line-state output. The downstream translation circuitry may be operable to process a transaction received on the host interface and to generate a transaction for the device interface. The upstream translation circuitry may be operable to process a transaction received on the device interface and to generate a transaction for the host interface. The host line-state state machine may be operable to set the host line-state output to a value that is one of: an SE0-state value, a J-state value, or a K-state value.

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing virtual device observation and debug network for high speed serial IOS.

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing high speed serial controller testing.

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing SoC coverage through virtual devices in PCIe and DMI controllers.

Abstract: An apparatus and method are described for a scalable testing agent. For example, one embodiment of a scalable test engine comprises: an input interface to receive commands and/or data from a processor core or an external test system, the commands and/or data to specify one or more test operations to be performed on one or more intellectual property (IP) blocks of a chip; a first circuit to establish communication with an IP block over an interconnect fabric, the first circuit to transmit the one or more test operations to the IP block responsive to the received commands and/or data, the IP block to process the test operations and generate results; and a second circuit to receive the results from the IP block over the interconnect fabric, the results to be provided from the second circuit to the processor core and/or the external test system for analysis.

Abstract: A method and system for high speed on chip testing for quality assurance. A multi-core system on a chip has a plurality of processing cores. The cores act as transaction agents with an auto-response unit fabricated on the chip at a chip boundary, the auto-response unit to provide a deterministic return value based on a logical address of a received read request.

Abstract: One embodiment provides an apparatus. The apparatus includes a functional test controller. The functional test controller includes controller logic to receive communication protocol-specific data comprising a packet header from a tester; a protocol buffer to store the packet header; and a pseudorandom bit sequence (PRBS) generator to generate a PRBS. The controller logic is to combine the packet header and the PRBS into a packet and to provide the packet to an input/output (I/O) controller under test.

Abstract: Described is a signature accumulator with a first set of logic devices, a second set of logic devices, and a memory device. The first set of logic devices includes compaction logic that couples an N-bit input bus to a K-bit first intermediate bus. The second set of logic devices includes commutative arithmetic operation logic that couples both the K-bit first intermediate bus and a K-bit signature bus to a K-bit second intermediate bus. The memory storage device includes a storage element that couples the K-bit second intermediate bus to the K-bit signature bus. The K-bit signature bus is also coupled to a valid-data input signal path.