Patents by Inventor Lan Lin
Lan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12255062Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.Type: GrantFiled: November 14, 2023Date of Patent: March 18, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
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Publication number: 20250015023Abstract: The invention provides a semiconductor structure, which comprises a plurality of metal circuit layers stacked with each other, the multi-layer metal circuit layer comprises an aluminum circuit layer which is located at the position closest to a surface among the plurality of circuit layers, the material of the aluminum circuit layer is made of aluminum, and the aluminum circuit layer comprises a concave portion.Type: ApplicationFiled: August 2, 2023Publication date: January 9, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chiu-Jung Chiu, Chung-Hsing Kuo, Chun-Ting Yeh, Chuan-Lan Lin, Yu-Ping Wang, Yu-Chun Chen
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Publication number: 20240429093Abstract: A method for fabricating a semiconductor device includes the steps of first defining a scribe line on a front side of a wafer, in which the wafer includes an inter-metal dielectric (IMD) layer disposed on a substrate and an alternating stack disposed on the IMD layer. Next, part of the alternating stack is removed to form a trench on the front side of the wafer, a dielectric layer is formed in the trench, and then a dicing process is performed along the scribe line from a back side of the wafer to divide the wafer into chips.Type: ApplicationFiled: July 21, 2023Publication date: December 26, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chien-Ting Lin, Kai-Kuang Ho, Chuan-Lan Lin, Yu-Ping Wang, Chu-Fu Lin, Yi-Feng Hsu, Yu-Jie Lin
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Publication number: 20240371695Abstract: A method for fabricating a semiconductor device includes the steps of first providing a wafer, forming a scribe line on a front side of the wafer, performing a plasma dicing process to dice the wafer along the scribe line without separating the wafer completely, performing a laminating process to form a tape on the front side of the wafer, performing a grinding process on a backside of the wafer, and then performing an expanding process to divide the wafer into chips.Type: ApplicationFiled: June 1, 2023Publication date: November 7, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chuan-Lan Lin, Yu-Ping Wang, Chien-Ting Lin, Chu-Fu Lin, Chun-Ting Yeh, Chung-Hsing Kuo
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Publication number: 20240373074Abstract: Systems, methods and apparatuses are described herein for accessing image data that comprises a plurality of macropixels, wherein the image data may be generated using a device comprising a lenslet array. The image data may be decomposed into a plurality of components using Kronecker product singular value decomposition (KP-SVD). Each component of the plurality of components may be encoded. Each encoded component of the plurality of components may be transmitted to cause display of reconstructed image data based on decoding each encoded component of the plurality of components.Type: ApplicationFiled: May 3, 2023Publication date: November 7, 2024Inventors: Ting-Lan Lin, Tao Chen
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Publication number: 20240315095Abstract: A semiconductor device includes a substrate having a bonding area and a pad area, a first inter-metal dielectric (IMD) layer on the substrate, a metal interconnection in the first IMD layer, a first pad on the bonding area and connected to the metal interconnection, and a second pad on the pad area and connected to the metal interconnection. Preferably, the first pad includes a first portion connecting the metal interconnection and a second portion on the first portion, and the second pad includes a third portion connecting the metal interconnection and a fourth portion on the third portion, in which top surfaces of the second portion and the fourth portion are coplanar.Type: ApplicationFiled: April 18, 2023Publication date: September 19, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chuan-Lan Lin, Yu-Ping Wang, Chien-Ting Lin, Chu-Fu Lin, Chun-Ting Yeh, Chung-Hsing Kuo, Yi-Feng Hsu
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Publication number: 20240162401Abstract: A method for fabricating a micro display device includes the steps of providing a wafer comprising a first area, a second area, and a third area, forming first bonding pads on the first area, forming second bonding pads on the second area, and forming third bonding pads on the third area. Preferably, the first bonding pads and the second bonding pads are made of different materials and the first bonding pads and the third bonding pads are made of different materials.Type: ApplicationFiled: December 9, 2022Publication date: May 16, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chuan-Lan Lin, Yu-Ping Wang, Chien-Ting Lin, Chun-Ting Yeh
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Publication number: 20240087879Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.Type: ApplicationFiled: November 14, 2023Publication date: March 14, 2024Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
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Patent number: 11854795Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.Type: GrantFiled: March 21, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
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Patent number: 11847083Abstract: The disclosure provides a daisy-chain serial peripheral interface (SPI) integrated circuit (IC) and an operation method thereof. The daisy-chain SPI IC includes a first MISO interface circuit, a second MISO interface circuit, a first data enable (DE) interface circuit, and a second DE interface circuit. When the daisy-chain SPI IC is a target slave circuit selected by a master IC for reading target data, the first DE interface circuit outputs a DE signal to the master IC, and the first MISO interface circuit sends back the target data to the master IC based on the timing of the DE signal. When the daisy-chain SPI IC is not the target slave circuit, the signal received by the second DE interface circuit is transmitted to the first DE interface circuit, and the data received by the second MISO interface circuit is transmitted to the first MISO interface circuit.Type: GrantFiled: December 16, 2021Date of Patent: December 19, 2023Assignee: HIMAX TECHNOLOGIES LIMITEDInventors: Shan-Chieh Wen, Ming-Huai Weng, Guei-Lan Lin, Che-Hao Chiang, Chi-Cheng Lin
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Patent number: 11847077Abstract: A serial peripheral interface (SPI) integrated circuit (IC) and an operation method thereof are provided. A SPI architecture includes a master IC and a slave IC. When the SPI IC is a master IC, the SPI IC generates first command information for a slave IC, generates first debugging information corresponding to the first command information, and sends the first command information and the first debugging information to the slave IC through a SPI channel. When the SPI IC is the slave IC, the SPI IC receives second command information and second debugging information sent by the master IC through the SPI channel and checks the second command information by using the second debugging information. When the SPI IC is a target slave circuit selected by the master IC, the SPI IC executes the second command information under a condition that the second command information is checked and is correct.Type: GrantFiled: December 6, 2021Date of Patent: December 19, 2023Assignee: HIMAX TECHNOLOGIES LIMITEDInventors: Shan-Chieh Wen, Ming-Huai Weng, Guei-Lan Lin, Che-Hao Chiang, Chi-Cheng Lin
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Patent number: 11819614Abstract: The present invention discloses a patient interface having an adaptive system, a respiratory mask and a cushion module adapted with the adaptive system. The adaptive system includes a forehead pressure diffusing portion, a cheek buffering portion and a connecting portion. The forehead pressure diffusing portion is disposed in a frame module. The cheek buffering portion is disposed in a cushion module. The connecting portion is positioned between the forehead pressure diffusing portion and the cheek buffering portion. The connecting portion is configured to transmit pressure between the forehead pressure diffusing portion and the cheek buffering portion. Thus, when a user wears a mask or other devices with the adaptive system, a force received by the face of the user could be automatically and appropriately distributed, further improving comfort of the wearer.Type: GrantFiled: June 26, 2019Date of Patent: November 21, 2023Assignee: APEX MEDICAL CORPInventors: Chun-hung Chen, Chih-tsan Chien, Pi-kai Lee, Yu-chen Liu, Chia-wei Huang, Shin-Lan Lin
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Patent number: 11735635Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor structure, a dielectric layer, a metal-semiconductor compound film and a cover layer. The semiconductor structure has an upper surface and a lateral surface. The dielectric layer encloses the lateral surface of the semiconductor structure and exposes the upper surface of the semiconductor structure. The metal-semiconductor compound film is on the semiconductor structure, wherein the dielectric layer exposes a portion of a surface of the metal-semiconductor compound film. The cover layer encloses the portion of the surface of the metal-semiconductor compound film exposed by the dielectric layer, and exposes the dielectric layer.Type: GrantFiled: July 19, 2021Date of Patent: August 22, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Han Tsao, Chih-Ming Chen, Han-Yu Chen, Szu-Yu Wang, Lan-Lin Chao, Cheng-Yuan Tsai
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Patent number: 11687475Abstract: The invention provides a large touch display integrated (LTDI) circuit and an operation method thereof. The LTDI circuit is suitable as a slave IC of an serial peripheral interface (SPI) architecture. The LTDI circuit includes an open-drain circuit and a reload circuit. An output terminal of the open-drain circuit is configured to be coupled to a correctness wire outside the LTDI circuit. The correctness wire is also coupled to an input terminal of a master IC of the SPI architecture, and a potential of the correctness wire is pulled up by a pull-up resistor. The reload circuit is coupled to an input terminal of the open-drain circuit. The reload circuit is configured to check a correctness of a boot up code from the master IC to generate a correctness check result. The reload circuit returns the correctness check result to the master IC via the open-drain circuit and the correctness wire.Type: GrantFiled: December 22, 2021Date of Patent: June 27, 2023Assignee: HIMAX TECHNOLOGIES LIMITEDInventors: Shan-Chieh Wen, Ming-Huai Weng, Guei-Lan Lin, Che-Hao Chiang, Chi-Cheng Lin
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Publication number: 20230195672Abstract: The disclosure provides a daisy-chain serial peripheral interface (SPI) integrated circuit (IC) and an operation method thereof. The daisy-chain SPI IC includes a first MISO interface circuit, a second MISO interface circuit, a first data enable (DE) interface circuit, and a second DE interface circuit. When the daisy-chain SPI IC is a target slave circuit selected by a master IC for reading target data, the first DE interface circuit outputs a DE signal to the master IC, and the first MISO interface circuit sends back the target data to the master IC based on the timing of the DE signal. When the daisy-chain SPI IC is not the target slave circuit, the signal received by the second DE interface circuit is transmitted to the first DE interface circuit, and the data received by the second MISO interface circuit is transmitted to the first MISO interface circuit.Type: ApplicationFiled: December 16, 2021Publication date: June 22, 2023Applicant: HIMAX TECHNOLOGIES LIMITEDInventors: Shan-Chieh Wen, Ming-Huai Weng, Guei-Lan Lin, Che-Hao Chiang, Chi-Cheng Lin
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Publication number: 20230195668Abstract: The invention provides a large touch display integrated (LTDI) circuit and an operation method thereof. The LTDI circuit is suitable as a slave IC of an serial peripheral interface (SPI) architecture. The LTDI circuit includes an open-drain circuit and a reload circuit. An output terminal of the open-drain circuit is configured to be coupled to a correctness wire outside the LTDI circuit. The correctness wire is also coupled to an input terminal of a master IC of the SPI architecture, and a potential of the correctness wire is pulled up by a pull-up resistor. The reload circuit is coupled to an input terminal of the open-drain circuit. The reload circuit is configured to check a correctness of a boot up code from the master IC to generate a correctness check result. The reload circuit returns the correctness check result to the master IC via the open-drain circuit and the correctness wire.Type: ApplicationFiled: December 22, 2021Publication date: June 22, 2023Applicant: HIMAX TECHNOLOGIES LIMITEDInventors: Shan-Chieh Wen, Ming-Huai Weng, Guei-Lan Lin, Che-Hao Chiang, Chi-Cheng Lin
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Publication number: 20230176985Abstract: A serial peripheral interface (SPI) integrated circuit (IC) and an operation method thereof are provided. A SPI architecture includes a master IC and a slave IC. When the SPI IC is a master IC, the SPI IC generates first command information for a slave IC, generates first debugging information corresponding to the first command information, and sends the first command information and the first debugging information to the slave IC through a SPI channel. When the SPI IC is the slave IC, the SPI IC receives second command information and second debugging information sent by the master IC through the SPI channel and checks the second command information by using the second debugging information. When the SPI IC is a target slave circuit selected by the master IC, the SPI IC executes the second command information under a condition that the second command information is checked and is correct.Type: ApplicationFiled: December 6, 2021Publication date: June 8, 2023Applicant: HIMAX TECHNOLOGIES LIMITEDInventors: Shan-Chieh Wen, Ming-Huai Weng, Guei-Lan Lin, Che-Hao Chiang, Chi-Cheng Lin
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Publication number: 20230121776Abstract: This invention refers to a method for maintaining machinery, comprising the steps of: a) determining, by a computer, when the machinery will need to be maintained, b) acquiring, by a computer, tasks to be executed by workers, c) generating, by a computer, a list of tasks for at least one of the workers, the list is generated including a task for maintaining the machinery as determined in step a) and including the tasks acquired in step b), d) maintaining the machinery based on the list of tasks for the one of the workers, wherein steps a) to c) are executed independently from each other.Type: ApplicationFiled: September 29, 2022Publication date: April 20, 2023Inventors: Cristina RODRIGUEZ-VERA, Lan LIN
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Patent number: 11508562Abstract: An embodiment low contamination chamber includes a gas inlet, an adjustable top electrode, and an adjustable bottom electrode. The low contamination chamber is configured to adjust a distance between the adjustable top electrode and the adjustable bottom electrode in response to a desired density of plasma and a measured density of plasma measured between the adjustable top electrode and the adjustable bottom electrode during a surface activation process. The low contamination chamber further includes an outlet.Type: GrantFiled: February 26, 2016Date of Patent: November 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ping-Yin Liu, Xin-Hua Huang, Lee-Chuan Tseng, Lan-Lin Chao
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Publication number: 20220308774Abstract: A method for managing HDD expanders in a cluster storage system is provided. The method according to one embodiment is implemented by each HDD expander connected indirectly to a host computer, and includes: indicating a device type not of HDD expander to the host computer when a device-type request originates from the host computer; and indicating a device type of HDD expander to a node that initiates the device-type request when otherwise.Type: ApplicationFiled: June 14, 2022Publication date: September 29, 2022Applicant: MITAC COMPUTING TECHNOLOGY COPROATIONInventors: Tsung-Yin LEE, Jen-Chih Lee, Yi-Lan Lin