Patents by Inventor Lan Lin

Lan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11959956
    Abstract: A circuit check method and an electronic apparatus applicable to a to-be-tested circuit are provided. The to-be-tested circuit has one or more first nodes related to a gate voltage of one or more transistor devices and a plurality of second nodes. The circuit check method includes: setting endpoint voltages of a plurality of input interface ports of the to-be-tested circuit; obtaining a first node voltage of the first node according to a conduction path of the to-be-tested circuit and the gate voltage of the transistor device; obtaining a second node voltage of each second node according to the conduction path, the endpoint voltages, and the first node voltage; and performing circuit static check on the to-be-tested circuit by applying the first node voltage and the second node voltage.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: April 16, 2024
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Yun-Jing Lin, Meng-Jung Lee, Yu-Lan Lo, Shu-Yi Kao
  • Publication number: 20240121358
    Abstract: In some examples, an electronic device includes a machine learning circuit to detect a user break from an online meeting based on a video stream. In some examples, the machine learning circuit is to send an indicator in response to detecting the user break. In some examples, the electronic device includes a processor coupled to the machine learning circuit. In some examples, the processor is to replace a portion of the video stream with substitute video in response to the indicator.
    Type: Application
    Filed: March 11, 2021
    Publication date: April 11, 2024
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Lan Wang, Qian Lin
  • Patent number: 11955608
    Abstract: A lithium precipitation detection method may include: sending, when a battery management module in the battery pack determines that a change in a charging voltage of the battery pack meets a predetermined condition, a charging request containing a first current to a charging pile for charging, and controlling the battery pack to be charged with the first current for a first predetermined duration and a second predetermined duration, where the first predetermined duration is equal to the second predetermined duration; obtaining, by the battery management module, a first voltage change amount within the first predetermined duration and a second voltage change amount within the second predetermined duration; and determining, when the battery management module determines that a difference between the second voltage change amount and the first voltage change amount is greater than a predetermined voltage threshold, that lithium precipitation occurs in the battery pack.
    Type: Grant
    Filed: October 12, 2023
    Date of Patent: April 9, 2024
    Assignee: CONTEMPORARY AMPEREX TECHNOLOGY CO., LIMITED
    Inventors: Lan Xie, Zhen Lin, Guangyu Xu, Shuai Song
  • Patent number: 11854795
    Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 11847083
    Abstract: The disclosure provides a daisy-chain serial peripheral interface (SPI) integrated circuit (IC) and an operation method thereof. The daisy-chain SPI IC includes a first MISO interface circuit, a second MISO interface circuit, a first data enable (DE) interface circuit, and a second DE interface circuit. When the daisy-chain SPI IC is a target slave circuit selected by a master IC for reading target data, the first DE interface circuit outputs a DE signal to the master IC, and the first MISO interface circuit sends back the target data to the master IC based on the timing of the DE signal. When the daisy-chain SPI IC is not the target slave circuit, the signal received by the second DE interface circuit is transmitted to the first DE interface circuit, and the data received by the second MISO interface circuit is transmitted to the first MISO interface circuit.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: December 19, 2023
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Shan-Chieh Wen, Ming-Huai Weng, Guei-Lan Lin, Che-Hao Chiang, Chi-Cheng Lin
  • Patent number: 11847077
    Abstract: A serial peripheral interface (SPI) integrated circuit (IC) and an operation method thereof are provided. A SPI architecture includes a master IC and a slave IC. When the SPI IC is a master IC, the SPI IC generates first command information for a slave IC, generates first debugging information corresponding to the first command information, and sends the first command information and the first debugging information to the slave IC through a SPI channel. When the SPI IC is the slave IC, the SPI IC receives second command information and second debugging information sent by the master IC through the SPI channel and checks the second command information by using the second debugging information. When the SPI IC is a target slave circuit selected by the master IC, the SPI IC executes the second command information under a condition that the second command information is checked and is correct.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: December 19, 2023
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Shan-Chieh Wen, Ming-Huai Weng, Guei-Lan Lin, Che-Hao Chiang, Chi-Cheng Lin
  • Patent number: 11819614
    Abstract: The present invention discloses a patient interface having an adaptive system, a respiratory mask and a cushion module adapted with the adaptive system. The adaptive system includes a forehead pressure diffusing portion, a cheek buffering portion and a connecting portion. The forehead pressure diffusing portion is disposed in a frame module. The cheek buffering portion is disposed in a cushion module. The connecting portion is positioned between the forehead pressure diffusing portion and the cheek buffering portion. The connecting portion is configured to transmit pressure between the forehead pressure diffusing portion and the cheek buffering portion. Thus, when a user wears a mask or other devices with the adaptive system, a force received by the face of the user could be automatically and appropriately distributed, further improving comfort of the wearer.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: November 21, 2023
    Assignee: APEX MEDICAL CORP
    Inventors: Chun-hung Chen, Chih-tsan Chien, Pi-kai Lee, Yu-chen Liu, Chia-wei Huang, Shin-Lan Lin
  • Patent number: 11735635
    Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor structure, a dielectric layer, a metal-semiconductor compound film and a cover layer. The semiconductor structure has an upper surface and a lateral surface. The dielectric layer encloses the lateral surface of the semiconductor structure and exposes the upper surface of the semiconductor structure. The metal-semiconductor compound film is on the semiconductor structure, wherein the dielectric layer exposes a portion of a surface of the metal-semiconductor compound film. The cover layer encloses the portion of the surface of the metal-semiconductor compound film exposed by the dielectric layer, and exposes the dielectric layer.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: August 22, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Han Tsao, Chih-Ming Chen, Han-Yu Chen, Szu-Yu Wang, Lan-Lin Chao, Cheng-Yuan Tsai
  • Patent number: 11687475
    Abstract: The invention provides a large touch display integrated (LTDI) circuit and an operation method thereof. The LTDI circuit is suitable as a slave IC of an serial peripheral interface (SPI) architecture. The LTDI circuit includes an open-drain circuit and a reload circuit. An output terminal of the open-drain circuit is configured to be coupled to a correctness wire outside the LTDI circuit. The correctness wire is also coupled to an input terminal of a master IC of the SPI architecture, and a potential of the correctness wire is pulled up by a pull-up resistor. The reload circuit is coupled to an input terminal of the open-drain circuit. The reload circuit is configured to check a correctness of a boot up code from the master IC to generate a correctness check result. The reload circuit returns the correctness check result to the master IC via the open-drain circuit and the correctness wire.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: June 27, 2023
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Shan-Chieh Wen, Ming-Huai Weng, Guei-Lan Lin, Che-Hao Chiang, Chi-Cheng Lin
  • Publication number: 20230195672
    Abstract: The disclosure provides a daisy-chain serial peripheral interface (SPI) integrated circuit (IC) and an operation method thereof. The daisy-chain SPI IC includes a first MISO interface circuit, a second MISO interface circuit, a first data enable (DE) interface circuit, and a second DE interface circuit. When the daisy-chain SPI IC is a target slave circuit selected by a master IC for reading target data, the first DE interface circuit outputs a DE signal to the master IC, and the first MISO interface circuit sends back the target data to the master IC based on the timing of the DE signal. When the daisy-chain SPI IC is not the target slave circuit, the signal received by the second DE interface circuit is transmitted to the first DE interface circuit, and the data received by the second MISO interface circuit is transmitted to the first MISO interface circuit.
    Type: Application
    Filed: December 16, 2021
    Publication date: June 22, 2023
    Applicant: HIMAX TECHNOLOGIES LIMITED
    Inventors: Shan-Chieh Wen, Ming-Huai Weng, Guei-Lan Lin, Che-Hao Chiang, Chi-Cheng Lin
  • Publication number: 20230195668
    Abstract: The invention provides a large touch display integrated (LTDI) circuit and an operation method thereof. The LTDI circuit is suitable as a slave IC of an serial peripheral interface (SPI) architecture. The LTDI circuit includes an open-drain circuit and a reload circuit. An output terminal of the open-drain circuit is configured to be coupled to a correctness wire outside the LTDI circuit. The correctness wire is also coupled to an input terminal of a master IC of the SPI architecture, and a potential of the correctness wire is pulled up by a pull-up resistor. The reload circuit is coupled to an input terminal of the open-drain circuit. The reload circuit is configured to check a correctness of a boot up code from the master IC to generate a correctness check result. The reload circuit returns the correctness check result to the master IC via the open-drain circuit and the correctness wire.
    Type: Application
    Filed: December 22, 2021
    Publication date: June 22, 2023
    Applicant: HIMAX TECHNOLOGIES LIMITED
    Inventors: Shan-Chieh Wen, Ming-Huai Weng, Guei-Lan Lin, Che-Hao Chiang, Chi-Cheng Lin
  • Publication number: 20230176985
    Abstract: A serial peripheral interface (SPI) integrated circuit (IC) and an operation method thereof are provided. A SPI architecture includes a master IC and a slave IC. When the SPI IC is a master IC, the SPI IC generates first command information for a slave IC, generates first debugging information corresponding to the first command information, and sends the first command information and the first debugging information to the slave IC through a SPI channel. When the SPI IC is the slave IC, the SPI IC receives second command information and second debugging information sent by the master IC through the SPI channel and checks the second command information by using the second debugging information. When the SPI IC is a target slave circuit selected by the master IC, the SPI IC executes the second command information under a condition that the second command information is checked and is correct.
    Type: Application
    Filed: December 6, 2021
    Publication date: June 8, 2023
    Applicant: HIMAX TECHNOLOGIES LIMITED
    Inventors: Shan-Chieh Wen, Ming-Huai Weng, Guei-Lan Lin, Che-Hao Chiang, Chi-Cheng Lin
  • Publication number: 20230121776
    Abstract: This invention refers to a method for maintaining machinery, comprising the steps of: a) determining, by a computer, when the machinery will need to be maintained, b) acquiring, by a computer, tasks to be executed by workers, c) generating, by a computer, a list of tasks for at least one of the workers, the list is generated including a task for maintaining the machinery as determined in step a) and including the tasks acquired in step b), d) maintaining the machinery based on the list of tasks for the one of the workers, wherein steps a) to c) are executed independently from each other.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 20, 2023
    Inventors: Cristina RODRIGUEZ-VERA, Lan LIN
  • Patent number: 11508562
    Abstract: An embodiment low contamination chamber includes a gas inlet, an adjustable top electrode, and an adjustable bottom electrode. The low contamination chamber is configured to adjust a distance between the adjustable top electrode and the adjustable bottom electrode in response to a desired density of plasma and a measured density of plasma measured between the adjustable top electrode and the adjustable bottom electrode during a surface activation process. The low contamination chamber further includes an outlet.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ping-Yin Liu, Xin-Hua Huang, Lee-Chuan Tseng, Lan-Lin Chao
  • Publication number: 20220310449
    Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.
    Type: Application
    Filed: June 16, 2022
    Publication date: September 29, 2022
    Inventors: Hsun-Chung Kuang, Yen-Chang Chu, Cheng-Tai Hsiao, Ping-Yin Liu, Lan-Lin Chao, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20220308774
    Abstract: A method for managing HDD expanders in a cluster storage system is provided. The method according to one embodiment is implemented by each HDD expander connected indirectly to a host computer, and includes: indicating a device type not of HDD expander to the host computer when a device-type request originates from the host computer; and indicating a device type of HDD expander to a node that initiates the device-type request when otherwise.
    Type: Application
    Filed: June 14, 2022
    Publication date: September 29, 2022
    Applicant: MITAC COMPUTING TECHNOLOGY COPROATION
    Inventors: Tsung-Yin LEE, Jen-Chih Lee, Yi-Lan Lin
  • Patent number: 11435915
    Abstract: A method for managing HDD expanders in a cluster storage system is provided. The method according to one embodiment is implemented by each of the HDD expanders, and includes: indicating a device type of HDD expander to a parent node thereof when a device-type request originates from the parent node; and indicating a device type not of HDD expander to the parent node otherwise. The method according to another embodiment is implemented by each HDD expander connected indirectly to a root node, and includes: indicating a device type not of HDD expander to the root node when a device-type request originates from the root node; and indicating a device type of HDD expander to a node that initiates the device-type request otherwise.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: September 6, 2022
    Assignee: MITAC COMPUTING TECHNOLOGY CORPORATION
    Inventors: Tsung-Yin Lee, Jen-Chih Lee, Yi-Lan Lin
  • Publication number: 20220273899
    Abstract: The present invention provides a patient interface including a cushion assembly, a headgear assembly, an elbow assembly and transition ring structure and a headgear secure assembly. The cushion assembly, the elbow assembly and the headgear secure assembly are assembled together by the transition ring structure. The cushion assembly is sealed with a face of a patient when in use. The headgear secure assembly is for connecting the headgear so as to secure the patient interface at the face of the patient when in use. The cushion assembly is provided with a cylindrical wall for delivering an air flow, and the cylindrical wall projects in two opposite directions along an axis of an opening thereof, so as to provide an air flow of a breathing chamber with a flow diversion guiding effect. Thus, the patient interface can be worn and used with better comfort and convenience.
    Type: Application
    Filed: February 9, 2022
    Publication date: September 1, 2022
    Inventors: SHIN-LAN LIN, YI-TING TSENG, SHU-CHI LIN, CHIH-TSAN CHIEN
  • Publication number: 20220268774
    Abstract: The present invention relates to a method of elevating prediction accuracy of grouping subjects with severe dengue infection. In the method, a non-structural protein 1 (NS1) and an endogenous anti-NS1 antibody of dengue virus in an ex vivo biological specimen are detected and crossly compared, leading in reduce of false negative rates of testing results, as well as elevating grouping accuracy of patients with severe dengue infection.
    Type: Application
    Filed: November 23, 2021
    Publication date: August 25, 2022
    Inventors: Tzong-Shiann HO, Ya-Lan LIN, Hong-Jyun HUANG, Yung-Chun CHUANG, Yu-Wei CHENG
  • Publication number: 20220216052
    Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.
    Type: Application
    Filed: March 21, 2022
    Publication date: July 7, 2022
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen