Patents by Inventor Lan Lin

Lan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9735033
    Abstract: An apparatus for cleaning a wafer includes a wafer station configured to hold the wafer, and a first and a second dispensing system. The first dispensing system includes a first swivel arm, and a first nozzle on the first swivel arm, wherein the first swivel arm is configured to move the first nozzle over and aside of the wafer. The first dispensing system includes first storage tank connected to the first nozzle, with the first nozzle configured to dispense a solution in the first storage tank. The second dispensing system includes a second swivel arm, and a second nozzle on the second swivel arm, wherein the second swivel arm is configured to move the second nozzle over and aside of the wafer. The second dispensing system includes a second storage tank connected to the second nozzle, with the second nozzle configured to dispense a solution in the second storage tank.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: August 15, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Lan-Lin Chao
  • Patent number: 9725310
    Abstract: A micro electromechanical system (MEMS) device includes a MEMS section attached to a substrate, and a cap bonded to a first surface of the substrate. The MEMS device further includes a carrier bonded to a second surface of the substrate opposite the first surface, wherein the carrier is free of active devices, and the cap and the carrier define a vacuum region surrounding the MEMS section. The MEMS device further includes a bond pad on a surface of the carrier opposite the MEMS section, wherein the bond pad is electrically connected to the MEMS section.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: August 8, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-wen Cheng, Hung-Chia Tsai, Lan-Lin Chao, Yuan-Chih Hsieh, Ping-Yin Liu
  • Patent number: 9708179
    Abstract: In some embodiments, the present disclosure relates to a MEMs (microelectromechanical system) package device having a getter layer. The MEMs package includes a first substrate having a cavity located within an upper surface of the first substrate. The cavity has roughened interior surfaces. A getter layer is arranged onto the roughened interior surfaces of the cavity. A bonding layer is arranged on the upper surface of the first substrate on opposing sides of the cavity, and a second substrate bonded to the first substrate by the bonding layer. The second substrate is arranged over the cavity. The roughened interior surfaces of the cavity enables more effective absorption of residual gases, thereby increasing the efficiency of a gettering process.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: July 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yuan-Chih Hsieh, Li-Cheng Chu, Hung-Hua Lin, Chih-Jen Chan, Lan-Lin Chao
  • Publication number: 20170140955
    Abstract: A method includes placing a first wafer onto a surface of a first wafer chuck, the first wafer chuck including multiple first profile control zones separated by one or more shared flexible membranes. The method also includes setting a first profile of the surface of the first wafer chuck. Setting a first profile of the surface of the first wafer chuck includes adjusting a first volume of a first profile control zone of the multiple first profile control zones. Setting a first profile of the surface of the first wafer chuck also includes adjusting a second volume of a second profile control zone of the multiple first profile control zones, the first volume of the first profile control zone being adjusted independently from the second volume of the second profile control zone, and the second adjustable volume encircling the first adjustable volume.
    Type: Application
    Filed: January 27, 2017
    Publication date: May 18, 2017
    Inventors: Ping-Yin Liu, Yen-Chang Chu, Xin-Hua Huang, Lan-Lin Chao, Yeur-Luen Tu, Ru-Liang Lee
  • Patent number: 9646860
    Abstract: Alignment systems, and wafer bonding alignment systems and methods are disclosed. In some embodiments, an alignment system for a wafer bonding system includes means for monitoring an alignment of a first wafer and a second wafer, and means for adjusting a position of the second wafer. The alignment system includes means for feeding back a relative position of the first wafer and the second wafer to the means for adjusting the position of the second wafer before and during a bonding process for the first wafer and the second wafer.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: May 9, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xin-Hua Huang, Xiaomeng Chen, Ping-Yin Liu, Lan-Lin Chao
  • Patent number: 9611141
    Abstract: The present disclosure provides a device having a doped active region disposed in a substrate. The doped active region having an elongate shape and extends in a first direction. The device also includes a plurality of first metal gates disposed over the active region such that the first metal gates each extend in a second direction different from the first direction. The plurality of first metal gates includes an outer-most first metal gate having a greater dimension measured in the second direction than the rest of the first metal gates. The device further includes a plurality of second metal gates disposed over the substrate but not over the doped active region. The second metal gates contain different materials than the first metal gates. The second metal gates each extend in the second direction and form a plurality of respective N/P boundaries with the first metal gates.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: April 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Yin Liu, Li-Cheng Chu, Hung-Hua Lin, Shang-Ying Tsai, Yuan-Chih Hsieh, Jung-Huei Peng, Lan-Lin Chao, Chia-Shiung Tsai, Chun-Wen Cheng
  • Publication number: 20170091289
    Abstract: An apparatus and a method for executing an automated analysis of analysis input data (e.g. social media data and/or On-Board-Diagnosis data) for product failure detection is proposed.
    Type: Application
    Filed: September 15, 2016
    Publication date: March 30, 2017
    Inventors: Anthony Emeka OHAZULIKE, Andrea TOMATIS, Lan LIN
  • Publication number: 20170077062
    Abstract: An apparatus includes a bottom stage configured to hold a bottom surface of a substrate stack including at least two substrates, a top stage configured to hold a top surface of the substrate stack, and at least one blade configured to be inserted between two adjacent substrates of the substrate stack, wherein the at least one blade has a pointed tip in plan view and has a channel configured to inject air or fluid.
    Type: Application
    Filed: November 8, 2016
    Publication date: March 16, 2017
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Lan-Lin Chao, Chia-Shiung Tsai
  • Publication number: 20170069593
    Abstract: A package component includes a surface dielectric layer including a planar top surface, a metal pad in the surface dielectric layer and including a second planar top surface level with the planar top surface, and an air trench on a side of the metal pad. The sidewall of the metal pad is exposed to the air trench.
    Type: Application
    Filed: November 21, 2016
    Publication date: March 9, 2017
    Inventors: Bruce C.S. Chou, Chen-Jong Wang, Ping-Yin Liu, Jung-Kuo Tu, Tsung-Te Chou, Xin-Hua Huang, Hsun-Chung Kuang, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 9576827
    Abstract: A system for and a method of bonding a first wafer to a second wafer are provided. A second wafer chuck has a second surface, a profile of the second surface being adjustable by a profile control layer. The first wafer is placed on a first surface of a first wafer chuck, and the second wafer is placed on the second surface of the second wafer chuck. The first wafer and the second wafer are warped prior to bonding to form a first warped wafer and a second warped wafer, respectively. The first warped wafer is bonded to the second warped wafer.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: February 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Yin Liu, Yen-Chang Chu, Xin-Hua Huang, Lan-Lin Chao, Yeur-Luen Tu, Ru-Liang Lee
  • Publication number: 20170047260
    Abstract: Presented herein is a device comprising a common node disposed in a first wafer a test node disposed in a first wafer and having a plurality of test pads exposed at a first surface of the first wafer. The test node also has test node lines connected to the test pads and that are separated by a first spacing and extend to a second surface of the first wafer. A comb is disposed in a second wafer and has a plurality of comb lines having a second spacing different from the first spacing. Each of the comb lines has a first surface exposed at a first side of the second wafer. The comb lines provide an indication of an alignment of the first wafer and second wafer by a number or arrangement of connections made by the plurality of comb lines between the test node lines and the common node.
    Type: Application
    Filed: October 24, 2016
    Publication date: February 16, 2017
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Lan-Lin Chao
  • Publication number: 20170039628
    Abstract: An image processing method. The method includes receiving, at a client terminal, a user request for displaying one or more outfit designs; identifying at least one matching condition associated with the outfit designs; sending a request for image information to a server, wherein the request includes the at least one matching condition; receiving the image information from the server, wherein the image information includes three-dimensional image information of an apparel item and one or more matching apparel items; and displaying one or more outfit images based on the three-dimensional image information and a preset template.
    Type: Application
    Filed: August 5, 2016
    Publication date: February 9, 2017
    Inventors: Xin WANG, Lan LIN, Fang GAO, Ying WANG, Jing LIU
  • Publication number: 20170004964
    Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.
    Type: Application
    Filed: September 19, 2016
    Publication date: January 5, 2017
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 9533876
    Abstract: A method includes forming a MEMS device, forming a bond layer adjacent the MEMS device, and forming a protection layer over the bond layer. The steps of forming the bond layer and the protection layer include in-situ deposition of the bond layer and the protection layer.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: January 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Yin Liu, Xin-Hua Huang, Hsin-Ting Huang, Yuan-Chih Hsieh, Jung-Huei Peng, Lan-Lin Chao, Chia-Shiung Tsai, Chun-Wen Cheng
  • Patent number: 9527188
    Abstract: A grinding wheel for wafer edge trimming includes a head having an open side and an abrasive end bonded around an edge of the open side of the head. The abrasive end is arranged to have multiple simultaneous contacts around a wafer edge during the wafer edge trimming.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: December 27, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai
  • Publication number: 20160358882
    Abstract: A semiconductor device and a method of fabricating the same are introduced. In an embodiment, one or more passivation layers are formed over a first substrate. Recesses are formed in the passivation layers and one or more conductive pads are formed in the recesses. One or more barrier layers are formed between the passivation layers and the conductive pads. The conductive pads of the first substrate are aligned to the conductive pads of a second substrate and are bonded using a direct bonding method.
    Type: Application
    Filed: August 16, 2016
    Publication date: December 8, 2016
    Inventors: Ping-Yin Liu, Lan-Lin Chao, Cheng-Tai Hsiao, Xin-Hua Huang, Hsun-Chung Kuang
  • Publication number: 20160351422
    Abstract: An apparatus for cleaning a wafer includes a wafer station configured to hold the wafer, and a first and a second dispensing system. The first dispensing system includes a first swivel arm, and a first nozzle on the first swivel arm, wherein the first swivel arm is configured to move the first nozzle over and aside of the wafer. The first dispensing system includes first storage tank connected to the first nozzle, with the first nozzle configured to dispense a solution in the first storage tank. The second dispensing system includes a second swivel arm, and a second nozzle on the second swivel arm, wherein the second swivel arm is configured to move the second nozzle over and aside of the wafer. The second dispensing system includes a second storage tank connected to the second nozzle, with the second nozzle configured to dispense a solution in the second storage tank.
    Type: Application
    Filed: July 1, 2016
    Publication date: December 1, 2016
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Lan-Lin Chao
  • Patent number: 9508586
    Abstract: A method includes receiving a wafer stack having at least two wafers bonded together. At least one blade is inserted between a first wafer of the at least two wafers and a second wafer of the at least two wafers. The blade has a channel configured to inject air or fluid. The first wafer is debonded from the second wafer using the at least one blade. In another embodiment, a detacher having a convex bottom surface is attached to the wafer stack. The first wafer is debonded from the second wafer using the detacher.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: November 29, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Lan-Lin Chao, Chia-Shiung Tsai
  • Patent number: 9502396
    Abstract: A package component includes a surface dielectric layer including a planar top surface, a metal pad in the surface dielectric layer and including a second planar top surface level with the planar top surface, and an air trench on a side of the metal pad. The sidewall of the metal pad is exposed to the air trench.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: November 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bruce C. S. Chou, Chen-Jong Wang, Ping-Yin Liu, Jung-Kuo Tu, Tsung-Te Chou, Xin-Hua Huang, Hsun-Chung Kuang, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 9478471
    Abstract: Presented herein is a device comprising a common node disposed in a first wafer' a test node disposed in a first wafer and having a plurality of test pads exposed at a first surface of the first wafer. The test node also has test node lines connected to the test pads and that are separated by a first spacing and extend to a second surface of the first wafer. A comb is disposed in a second wafer and has a plurality of comb lines having a second spacing different from the first spacing. Each of the comb lines has a first surface exposed at a first side of the second wafer. The comb lines provide an indication of an alignment of the first wafer and second wafer by a number or arrangement of connections made by the plurality of comb lines between the test node lines and the common node.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: October 25, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Lan-Lin Chao