Patents by Inventor Lan Lin
Lan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220208607Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.Type: ApplicationFiled: March 17, 2022Publication date: June 30, 2022Inventors: Hsun-Chung Kuang, Yen-Chang Chu, Cheng-Tai Hsiao, Ping-Yin Liu, Lan-Lin Chao, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
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Patent number: 11282697Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.Type: GrantFiled: September 12, 2019Date of Patent: March 22, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
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Patent number: 11269132Abstract: A display device includes a light source arranged to emit light along a first edge of the display device, and aa light guide plate arranged go receive the emitted light at a minor surface of the light guide plate. The light guide plate includes prismatic elements configured to reemit the light out a first major surface of the light guide plate. A first region of the light guide plate has a first portion of the prismatic elements arranged in a first density to provide a first brightness of the reemitted light reemitted. A second region of the light guide plate has a second portion of the prismatic elements arranged in a second density to provide a second brightness of the reemitted light reemitted. The first region is provided substantially along a first edge of the first major surface, and the second region is provided along a second, a third, and a fourth edge of the first major surface. The first brightness is brighter than the second brightness.Type: GrantFiled: April 26, 2021Date of Patent: March 8, 2022Assignee: Dell Products L.P.Inventors: Yu-Lung Lin, Max Lu, How-Lan Lin, Dan Odell Boice, Asim Siddiqui
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Patent number: 11180167Abstract: A double-track vehicle, comprising upper and lower carriages, which are respectively a passenger carriage (1) for providing passenger seats and a cargo carriage (2) for placing cargo, the passenger carriage (1) and the cargo carriage (2) being respectively provided with a passenger door (3) for passengers to get on and off and a cargo door (4) for loading and unloading cargo. The vehicle carries out simultaneous transport of passengers and cargo, allowing for the function of the rail vehicle to no longer be singular and largely reducing transport and maintenance costs. At the same time, passenger transport and cargo transport are divided into two layers, which completely separates cargo transport and passenger transport, thereby providing passengers with a comfortable seating environment and improving seating safety.Type: GrantFiled: August 26, 2017Date of Patent: November 23, 2021Assignee: CRRC QINGDAO SIFANG CO., LTD.Inventors: Xiaojun Deng, Peng Lin, Liangkui Jiang, Li Dong, Huaxin Hu, Qingjing Dong, Lan Lin
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Publication number: 20210343849Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor structure, a dielectric layer, a metal-semiconductor compound film and a cover layer. The semiconductor structure has an upper surface and a lateral surface. The dielectric layer encloses the lateral surface of the semiconductor structure and exposes the upper surface of the semiconductor structure. The metal-semiconductor compound film is on the semiconductor structure, wherein the dielectric layer exposes a portion of a surface of the metal-semiconductor compound film. The cover layer encloses the portion of the surface of the metal-semiconductor compound film exposed by the dielectric layer, and exposes the dielectric layer.Type: ApplicationFiled: July 19, 2021Publication date: November 4, 2021Inventors: Chun-Han Tsao, Chih-Ming Chen, Han-Yu Chen, Szu-Yu Wang, Lan-Lin Chao, Cheng-Yuan Tsai
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Patent number: 11069785Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor structure, a dielectric layer, a metal-semiconductor compound film and a cover layer. The semiconductor structure has an upper surface and a lateral surface. The dielectric layer encloses the lateral surface of the semiconductor structure and exposes the upper surface of the semiconductor structure. The metal-semiconductor compound film is on the semiconductor structure, wherein the dielectric layer exposes a portion of a surface of the metal-semiconductor compound film. The cover layer encloses the portion of the surface of the metal-semiconductor compound film exposed by the dielectric layer, and exposes the dielectric layer.Type: GrantFiled: April 26, 2019Date of Patent: July 20, 2021Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Chun-Han Tsao, Chih-Ming Chen, Han-Yu Chen, Szu-Yu Wang, Lan-Lin Chao, Cheng-Yuan Tsai
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Patent number: 11014805Abstract: A method of making a semiconductor package includes bonding a carrier to a surface of the substrate, wherein the carrier is free of active devices, wherein the carrier includes a carrier bond pad on a surface of the carrier. The method further includes bonding a wafer bond pad of an active circuit wafer to the carrier bond pad, wherein the bonding of the wafer bond pad to the carrier bond pad comprises re-graining the wafer bond pad to form at least one grain boundary extending from the wafer bond pad to the carrier bond pad.Type: GrantFiled: August 19, 2019Date of Patent: May 25, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-wen Cheng, Hung-Chia Tsai, Lan-Lin Chao, Yuan-Chih Hsieh, Ping-Yin Liu
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Publication number: 20210151353Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.Type: ApplicationFiled: January 4, 2021Publication date: May 20, 2021Inventors: Hsun-Chung Kuang, Yen-Chang Chu, Cheng-Tai Hsiao, Ping-Yin Liu, Lan-Lin Chao, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
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Publication number: 20210013098Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.Type: ApplicationFiled: September 28, 2020Publication date: January 14, 2021Inventors: Hsun-Chung Kuang, Yen-Chang Chu, Cheng-Tai Hsiao, Ping-Yin Liu, Lan-Lin Chao, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
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Publication number: 20210004168Abstract: A method for managing HDD expanders in a cluster storage system is provided. The method according to one embodiment is implemented by each of the HDD expanders, and includes: indicating a device type of HDD expander to a parent node thereof when a device-type request originates from the parent node; and indicating a device type not of HDD expander to the parent node otherwise. The method according to another embodiment is implemented by each HDD expander connected indirectly to a root node, and includes: indicating a device type not of HDD expander to the root node when a device-type request originates from the root node; and indicating a device type of HDD expander to a node that initiates the device-type request otherwise.Type: ApplicationFiled: June 11, 2020Publication date: January 7, 2021Applicant: MITAC COMPUTING TECHNOLOGY CORPORATIONInventors: Tsung-Yin Lee, Jen-Chih Lee, Yi-Lan Lin
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Patent number: 10860013Abstract: Among other things, one or more techniques and/or systems are provided for providing recommendations to address design flaws of power system equipment and/or model design flaws for equipment model types of power system equipment. For example, historical sensor data and/or historical field test data, collected from power system equipment, may be analyzed to identify a design flaw of the power system equipment (e.g., a design flaw of a seal ring). A redesign cost to redesign the power system equipment, a failure impact of a failure from the design flaw, a maintenance repair and/or replacement cost, a manufacture alternative component cost to use an alternative component for manufacturing the power system equipment, and/or other factors may be taken into account to crate and provide a recommendation to address the design flaw.Type: GrantFiled: October 19, 2015Date of Patent: December 8, 2020Assignee: ABB Power Grids Switzerland AGInventors: Aldo Dagnino, Luiz V. Cheim, Lan Lin, Poorvi Patel, Asim Fazlagic
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Patent number: 10790189Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.Type: GrantFiled: October 2, 2018Date of Patent: September 29, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsun-Chung Kuang, Yen-Chang Chu, Cheng-Tai Hsiao, Ping-Yin Liu, Lan-Lin Chao, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
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Patent number: 10665449Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.Type: GrantFiled: September 19, 2016Date of Patent: May 26, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
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Publication number: 20200002161Abstract: A method of making a semiconductor package includes bonding a carrier to a surface of the substrate, wherein the carrier is free of active devices, wherein the carrier includes a carrier bond pad on a surface of the carrier. The method further includes bonding a wafer bond pad of an active circuit wafer to the carrier bond pad, wherein the bonding of the wafer bond pad to the carrier bond pad comprises re-graining the wafer bond pad to form at least one grain boundary extending from the wafer bond pad to the carrier bond pad.Type: ApplicationFiled: August 19, 2019Publication date: January 2, 2020Inventors: Chun-wen CHENG, Hung-Chia TSAI, Lan-Lin CHAO, Yuan-Chih HSIEH, Ping-Yin LIU
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Publication number: 20200001034Abstract: The present invention discloses a patient interface having an adaptive system, a respiratory mask and a cushion module adapted with the adaptive system. The adaptive system includes a forehead pressure diffusing portion, a cheek buffering portion and a connecting portion. The forehead pressure diffusing portion is disposed in a frame module. The cheek buffering portion is disposed in a cushion module. The connecting portion is positioned between the forehead pressure diffusing portion and the cheek buffering portion. The connecting portion is configured to transmit pressure between the forehead pressure diffusing portion and the cheek buffering portion. Thus, when a user wears a mask or other devices with the adaptive system, a force received by the face of the user could be automatically and appropriately distributed, further improving comfort of the wearer.Type: ApplicationFiled: June 26, 2019Publication date: January 2, 2020Inventors: Chun-hung Chen, Chih-tsan Chien, Pi-kai Lee, Yu-chen Liu, Chia-wei Huang, Shin-Lan Lin
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Publication number: 20200006052Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.Type: ApplicationFiled: September 12, 2019Publication date: January 2, 2020Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
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Publication number: 20190357444Abstract: A garden scissors of the present invention includes a chassis, a transmission mechanism, a driving line, and a cutter. The transmission mechanism is rotatably disposed to the chassis. The transmission mechanism includes a pulley portion, a gear portion, and a flywheel portion, which rotate simultaneously. The gear portion is located between the pulley portion and the flywheel portion. An end of the driving line is rolled on the pulley portion. The cutter has an engagement portion engaged with the gear portion. Thus, the pulley portion, the gear portion, and the cutter are rotated when the driving line is pulled away from the pulley portion, driving the cutter to pivot to cut branches. Therefore, the flywheel portion of the transmission mechanism laying on the chassis, supporting and balancing the force exerted on and the movements of the pulley portion and the gear portion. The structure of the garden scissors is then stabilized.Type: ApplicationFiled: May 28, 2018Publication date: November 28, 2019Inventor: Chu-Lan Lin
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Publication number: 20190259848Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor structure, a dielectric layer, a metal-semiconductor compound film and a cover layer. The semiconductor structure has an upper surface and a lateral surface. The dielectric layer encloses the lateral surface of the semiconductor structure and exposes the upper surface of the semiconductor structure. The metal-semiconductor compound film is on the semiconductor structure, wherein the dielectric layer exposes a portion of a surface of the metal-semiconductor compound film. The cover layer encloses the portion of the surface of the metal-semiconductor compound film exposed by the dielectric layer, and exposes the dielectric layer.Type: ApplicationFiled: April 26, 2019Publication date: August 22, 2019Inventors: Chun-Han TSAO, Chi-Ming CHEN, Han-Yu CHEN, Szu-Yu WANG, Lan-Lin CHAO, Cheng-Yuan TSAI
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Patent number: 10384933Abstract: A method of making a micro electromechanical system (MEMS) package includes patterning a substrate to form a MEMS section. The method further includes bonding a carrier to a surface of the substrate. The carrier is free of active devices. The carrier includes a carrier bond pad on a surface of the carrier opposite the MEMS section. The carrier bond pad is electrically connected to the MEMS section. The method further includes bonding a wafer bond pad of an active circuit wafer to the carrier bond pad. The bonding of the wafer bond pad to the carrier bond pad includes re-graining the wafer bond pad to form at least one grain boundary extending from the wafer bond pad to the carrier bond pad.Type: GrantFiled: July 7, 2017Date of Patent: August 20, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-wen Cheng, Hung-Chia Tsai, Lan-Lin Chao, Yuan-Chih Hsieh, Ping-Yin Liu
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Publication number: 20190241200Abstract: Provided are a railway vehicle carriage structure and a railway vehicle. Doors (9) enabling passengers to board and alight are provided on two sides of a vehicle body of at least one end part of a carriage (1, 2), a region directly between the doors is a vestibule (12), and the space of the vestibule (12) is substantially circular. This type of carriage structure enlarges the passing space in the vestibule (12) for people, can effectively relieve the state of overcrowding when a large number of people are boarding and alighting, and increases the comfort of passengers of railway vehicles.Type: ApplicationFiled: August 26, 2017Publication date: August 8, 2019Applicant: CRRC QINGDAO SIFANG CO., LTD.Inventors: Dawei CHEN, Huaxin HU, Qingjing DONG, Lan LIN