Patents by Inventor Lan Lin

Lan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130099355
    Abstract: A method includes forming a MEMS device, forming a bond layer adjacent the MEMS device, and forming a protection layer over the bond layer.
    Type: Application
    Filed: October 24, 2011
    Publication date: April 25, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Yin Liu, Xin-Hua Huang, Hsin-Ting Huang, Yuan-Chih Hsieh, Jung-Huei Peng, Lan-Lin Chao, Chia-Shiung Tsai, Chun-Wen Cheng
  • Publication number: 20130082338
    Abstract: A device includes a micro-electro-mechanical system (MEMS) device, which includes a movable element and a fixed element. The movable element and the fixed element form two capacitor plates of a capacitor, with an air-gap between the movable element and the fixed element acting as a capacitor insulator of the capacitor. At least one of the movable element and the fixed element has a rugged surface.
    Type: Application
    Filed: September 30, 2011
    Publication date: April 4, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lung Yuan Pan, Lan-Lin Chao, Chia-Shiung Tsai
  • Patent number: 8405169
    Abstract: A device is provided which includes a transparent substrate. An opaque layer is disposed on the transparent substrate. A conductive layer disposed on the opaque layer. The opaque layer and the conductive layer form a handling layer, which may be used to detect and/or align the transparent wafer during fabrication processes. In an embodiment, the conductive layer includes a highly-doped silicon layer. In an embodiment, the opaque layer includes a metal. In embodiment, the device may include a MEMs device.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: March 26, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Ren Cheng, Yi-Hsien Chang, Allen Timothy Chang, Ching-Ray Chen, Li-Cheng Chu, Hung-Hua Lin, Yuan-Chih Hsieh, Lan-Lin Chao
  • Publication number: 20120282420
    Abstract: An outer housing structure includes a soft polymer layer, a decorative layer and a plastic injection substrate. The soft polymer layer includes a three-dimensional texture surface. The decorative layer is disposed on a surface of the soft polymer layer, which is opposite to the three-dimensional texture surface. The plastic injection substrate is disposed the decorative layer, wherein the decorative layer is disposed between the soft polymer layer and the plastic injection substrate, and the plastic injection substrate and the decorative layer are bonded by a plastic injection process.
    Type: Application
    Filed: July 4, 2011
    Publication date: November 8, 2012
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Kuang-Cheng FAN, Yen-Jung CHEN, Shih-Wei LI, Hua-Lan LIN
  • Publication number: 20120256587
    Abstract: A display device for displaying information of a rechargeable battery of an electric vehicle and a charging module using the display device are disclosed in the present invention. The display device includes a battery capacity unit, a lifetime unit, an information collecting unit and a display unit. It can display the charging state, lifetime, cycle count and health state of the rechargeable battery. The charging module includes a power unit for providing power. It can display battery information when charging the rechargeable battery. The invention provides a convenient way to let customers know the status of the batteries of their electric vehicles and decide if the batteries need to be charged or replaced.
    Type: Application
    Filed: April 8, 2011
    Publication date: October 11, 2012
    Applicant: Go-Tech Energy Co., Ltd.
    Inventors: Tzu-Wen Soong, Hung-Lan Lin
  • Publication number: 20120244677
    Abstract: The present disclosure provides various methods for removing an anti-stiction layer. An exemplary method includes forming an anti-stiction layer over a substrate, including over a first substrate region of a first material and a second substrate region of a second material, wherein the second material is different than the first material; and selectively removing the anti-stiction layer from the second substrate region of the second material without using a mask.
    Type: Application
    Filed: March 24, 2011
    Publication date: September 27, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Wei Lin, Ping-Yin Liu, Lan-Lin Chao, Jung-Huei Peng, Chia-Shiung Tsai
  • Publication number: 20120235300
    Abstract: The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having via sidewall surfaces defined by a semiconductor substrate. The via sidewall surfaces have a first portion and a second portion. A conductive layer is disposed in the via on the first portion of the via sidewall surfaces, and a dielectric layer is disposed on the second portion of the via sidewall surfaces. The dielectric layer is disposed between the second portion of the via sidewall surfaces and the conductive layer. In an example, the dielectric layer is an oxide layer.
    Type: Application
    Filed: May 25, 2012
    Publication date: September 20, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Chih Hsieh, Richard Chu, Ming-Tung Wu, Martin Liu, Lan-Lin Chao, Chia-Shiung Tsai
  • Publication number: 20120238091
    Abstract: The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a method for forming a via structure includes forming a via in a semiconductor substrate, wherein via sidewalls of the via are defined by the semiconductor substrate; forming a dielectric layer on the via sidewalls; removing the dielectric layer from a portion of the via sidewalls; and forming a conductive layer to fill the via, wherein the conductive layer is disposed over the dielectric layer and the portion of the via sidewalls. In an example, the dielectric layer is an oxide layer.
    Type: Application
    Filed: May 25, 2012
    Publication date: September 20, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Chih Hsieh, Richard Chu, Ming-Tung Wu, Martin Liu, Lan-Lin Chao, Chia-Shiung Tsai
  • Patent number: 8254453
    Abstract: A multi-format video decoder includes a bitstream buffer, a system controller, a bitstream decoding unit, an intra mode decoding unit and a shared prediction module. The system controller selectively generates a first control signal or a second control signal according to a video bitstream. The bitstream decoding unit generates a decoding information signal according to the video bitstream when receiving the first control signal. The intra mode decoding unit generates an intra mode signal when receiving the second control signal. The shared prediction module performs an AC/DC prediction upon a current block of the video bitstream to generate a current first prediction result according to the decoding information signal and performs an intra prediction upon the current block to generate a current second prediction result according to the intra mode signal. The shared prediction module includes shared components being utilized in the AC/DC prediction and the intra prediction.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: August 28, 2012
    Assignee: Himax Media Solutions, Inc.
    Inventors: Chan-Shih Lin, Shu-Hsien Chou, Kuei-Lan Lin
  • Publication number: 20120184689
    Abstract: The present invention relates to a stationary phase composition. The composition comprises a support material, on which at least a divinylbenzene group and an acrylic group, and optionally a styrene group, are provided. Preferably, the acrylic group has an alkyl moiety of at least 4 carbon atoms. The composition can serve as a monolithic column for chromatographic separation. The composition exhibits an altered ?-? interaction with aromatic compounds, whereby the peak symmetry of aromatic compounds is improved during separation, the separation time is shortened and the occurrence of peak-overlapping and peak-tailing is prevented.
    Type: Application
    Filed: August 16, 2011
    Publication date: July 19, 2012
    Inventors: Hsi-Ya Huang, Yi-Jie Cheng, Chao-Hsiang Hsu, Wan-Ling Liu, Yi-Fen Hsu, Cheng-Lan Lin, Sze-Tsen Lee
  • Patent number: 8207595
    Abstract: A semiconductor device includes a substrate wafer, a dielectric layer overlying the substrate wafer, a patterned conductor layer in the dielectric layer, and a first barrier layer overlying the conductor layer. A silicon top wafer is bonded to the dielectric layer. A via is formed through the top wafer and a portion of the dielectric layer to the first barrier layer. A sidewall dielectric layer is formed along inner walls of the via, adjacent the top wafer to a distance below an upper surface of the top wafer, forming a sidewall dielectric layer shoulder. A sidewall barrier layer is formed inward of the sidewall dielectric layer, lining the via from the first barrier layer to the upper surface of the top wafer. A conductive layer fills the via and a top barrier layer is formed on the conductive layer, the sidewall barrier layer, and the top wafer.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: June 26, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yuan-Chih Hsieh, Richard Chu, Ming-Tung Wu, Martin Liu, Lan-Lin Chao, Chia-Shiung Tsai
  • Publication number: 20120148870
    Abstract: A bond free of an anti-stiction layer and bonding method is disclosed. An exemplary method includes forming a first bonding layer; forming an interlayer over the first bonding layer; forming an anti-stiction layer over the interlayer; and forming a liquid from the first bonding layer and interlayer, such that the anti-stiction layer floats over the first bonding layer. A second bonding layer can be bonded to the first bonding layer while the anti-stiction layer floats over the first bonding layer, such that a bond between the first and second bonding layers is free of the anti-stiction layer.
    Type: Application
    Filed: December 9, 2010
    Publication date: June 14, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ping-Yin Liu, Li-Cheng Chu, Hung-Hua Lin, Shang-Ying Tsai, Yuan-Chih Hsieh, Jung-Huei Peng, Lan-Lin Chao, Chia-Shiung Tsai, Chun-Wen Cheng
  • Publication number: 20120091598
    Abstract: A device is provided which includes a transparent substrate. An opaque layer is disposed on the transparent substrate. A conductive layer disposed on the opaque layer. The opaque layer and the conductive layer form a handling layer, which may be used to detect and/or align the transparent wafer during fabrication processes. In an embodiment, the conductive layer includes a highly-doped silicon layer. In an embodiment, the opaque layer includes a metal. In embodiment, the device may include a MEMs device.
    Type: Application
    Filed: October 15, 2010
    Publication date: April 19, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Ren Cheng, Yi-Hsien Chang, Allen Timothy Chang, Ching-Ray Chen, Li-Cheng Chu, Hung-Hua Lin, Yuan-Chih Hsieh, Lan-Lin Chao
  • Patent number: 8156410
    Abstract: A video decoder capable of generating a check data in response to a data selection code for debugging is disclosed. The video decoder includes a plurality of functional blocks, wherein each said plurality of functional blocks has a output signal to be used as an input signal for a next stage functional block; a multiplexer (209) that receives a plurality of data extracted from said plurality of output signals from said plurality of functional blocks, and outputs one of said plurality of data according to said data selection code; and a check logic (210) that generates said check data by calculating one of said plurality of data outputted from said multiplexer.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: April 10, 2012
    Assignee: Himax Technologies Limited
    Inventors: Chan-Shih Lin, Kuei-Lan Lin
  • Publication number: 20120080761
    Abstract: A semiconductor device includes a substrate wafer, a dielectric layer overlying the substrate wafer, a patterned conductor layer in the dielectric layer, and a first barrier layer overlying the conductor layer. A silicon top wafer is bonded to the dielectric layer. A via is formed through the top wafer and a portion of the dielectric layer to the first barrier layer. A sidewall dielectric layer is formed along inner walls of the via, adjacent the top wafer to a distance below an upper surface of the top wafer, forming a sidewall dielectric layer shoulder. A sidewall barrier layer is formed inward of the sidewall dielectric layer, lining the via from the first barrier layer to the upper surface of the top wafer. A conductive layer fills the via and a top barrier layer is formed on the conductive layer, the sidewall barrier layer, and the top wafer.
    Type: Application
    Filed: October 5, 2010
    Publication date: April 5, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Chih Hsieh, Richard Chu, Ming-Tung Wu, Martin Liu, Lan-Lin Chao, Chia-Shiung Tsai
  • Publication number: 20120025389
    Abstract: Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum-based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers.
    Type: Application
    Filed: July 29, 2010
    Publication date: February 2, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Richard Chu, Martin Liu, Chia-Hua Chu, Yuan-Chih Hsieh, Chung-Hsien Lin, Lan-Lin Chao, Chun-Wen Cheng, Mingo Liu
  • Publication number: 20110233621
    Abstract: The present disclosure provides a method of bonding a plurality of substrates. In an embodiment, a first substrate includes a first bonding layer. The second substrate includes a second bonding layer. The first bonding layer includes silicon; the second bonding layer includes aluminum. The first substrate and the second substrate are bonded forming a bond region having an interface between the first bonding layer and the second bonding layer. A device having a bonding region between substrates is also provided. The bonding region includes an interface between a layer including silicon and a layer including aluminum.
    Type: Application
    Filed: March 23, 2010
    Publication date: September 29, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Martin Liu, Richard Chu, Hung-Hua Lin, H. T. Huang, Jung-Huei Peng, Yuan-Chih Hsieh, Lan-Lin Chao, Chun-Wen Cheng, Chia-Shiung Tsai
  • Publication number: 20110194723
    Abstract: An exemplary magnetic diaphragm is applied to an electro-acoustic transducer. The magnetic diaphragm has a base formed with a magnetic layer thereon by a film deposition method. The base with the magnetic layer thus has magnetism to interference with a magnetic circuit of the electro-acoustic transducer. A manufacture method of the magnetic diaphragm is also disclosed.
    Type: Application
    Filed: February 10, 2010
    Publication date: August 11, 2011
    Inventors: Ching-Lan Lin, Hong-Ching Her
  • Publication number: 20110175947
    Abstract: A method for improving image stitch-in phenomenon is disclosed. The method includes the following steps. First, at least a first gray-scale line is inserted into the position of a corresponding number of scan line(s) in a frame. Then, at least a second gray-scale line is inserted into the position of a corresponding number of scan line(s) in the next frame. By inserting gray-scale line(s) into different positions sequentially, the image stitch-in phenomenon will not appear when changing a picture that has been displayed for a long time. The present invention can also improve the stitch-in phenomenon happening in an electronic photo frame and a liquid crystal display as well. Thus, the present invention is able to match the demand of human vision and improves the quality of visual display.
    Type: Application
    Filed: March 29, 2011
    Publication date: July 21, 2011
    Applicant: Chunghwa Picture Tubes, LTD.
    Inventors: Yi-Lan LIN, Kuo-Chao YEH, Hsiang-Lun LIU
  • Publication number: 20110176609
    Abstract: A multi-format video decoder includes a bitstream buffer, a system controller, a bitstream decoding unit, an intra mode decoding unit and a shared prediction module. The system controller selectively generates a first control signal or a second control signal according to a video bitstream. The bitstream decoding unit generates a decoding information signal according to the video bitstream when receiving the first control signal. The intra mode decoding unit generates an intra mode signal when receiving the second control signal. The shared prediction module performs an AC/DC prediction upon a current block of the video bitstream to generate a current first prediction result according to the decoding information signal and performs an intra prediction upon the current block to generate a current second prediction result according to the intra mode signal. The shared prediction module includes shared components being utilized in the AC/DC prediction and the intra prediction.
    Type: Application
    Filed: January 20, 2010
    Publication date: July 21, 2011
    Inventors: Chan-Shih Lin, Shu-Hsien Chou, Kuei-Lan Lin