Abstract: A composite vibration diaphragm fabrication method includes the steps of: (a) mixing a reinforcing material with a hot melt adhesive to form a first mixture and to let the reinforcing material be wrapped in the hot melt adhesive uniformly, (b) mixing the first mixture with a thermosetting adhesive to form a second mixture, (c) coating the second mixture on a vibration diaphragm material and then heating the second mixture coated vibration diaphragm material, and (d) cooling down the coated vibration diaphragm material in which the second mixture is cured and bonded to the vibration diaphragm material. Thus, when baking the second mixture, the internal hot melt adhesive will be melted and integrated with the thermosetting adhesive, and the thermosetting adhesive will also be cured, enabling the reinforcing material to be uniformly bonded to the vibration diaphragm to reinforce the strength and rigidity of the composite vibration diaphragm.

Abstract: Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.

Abstract: A battery sharing system is disclosed in the present invention. The system includes a number of rechargeable battery packs, at least one charging device and a monitoring device. A portion of rechargeable battery packs are provided to users for use under a sharing mode. When one used rechargeable battery pack is in low status, the user exchanges the used rechargeable battery pack with another one of the rechargeable battery packs which is fully charged.

Abstract: A method includes forming a MEMS device, forming a bond layer adjacent the MEMS device, and forming a protection layer over the bond layer.

Abstract: The embodiments of diffusion barrier layer described above provide mechanisms for forming a copper diffusion barrier layer to prevent device degradation for hybrid bonding of wafers. The diffusion barrier layer(s) encircles the copper-containing conductive pads used for hybrid bonding. The diffusion barrier layer can be on one of the two bonding wafers or on both bonding wafers.

Abstract: A backside illuminated image sensor comprises a photodiode and a first transistor located in a first chip, wherein the first transistor is electrically coupled to the photodiode. The backside illuminated image sensor further comprises a second transistor formed in a second chip and a plurality of logic circuits formed in a third chip, wherein the second chip is stacked on the first chip and the third chip is stacked on the second chip. The logic circuit, the second transistor and the first transistor are coupled to each other through a plurality of boding pads and through vias.

Abstract: A composite diaphragm is provided to include a base layer and a micro-nanometer ceramic layer disposed on the surface of the base layer. The micro-nanometer ceramic is a structural material that has great stiffness and toughness, such that the composite diaphragm made of micro-nanometer ceramic manifests characteristics of high stiffness, high toughness, and great ductility. Thus, the composite diaphragm allows large deformation at room temperature to achieve high capability of producing high-definition tone.

Abstract: A semiconductor device and a method of fabricating the same are introduced. In an embodiment, one or more passivation layers are formed over a first substrate. Recesses are formed in the passivation layers and one or more conductive pads are formed in the recesses. One or more barrier layers are formed between the passivation layers and the conductive pads. The conductive pads of the first substrate are aligned to the conductive pads of a second substrate and are bonded using a direct bonding method.

Abstract: Presented herein is a device comprising a common node disposed in a first wafer a test node disposed in a first wafer and having a plurality of test pads exposed at a first surface of the first wafer. The test node also has test node lines connected to the test pads and that are separated by a first spacing and extend to a second surface of the first wafer. A comb is disposed in a second wafer and has a plurality of comb lines having a second spacing different from the first spacing. Each of the comb lines has a first surface exposed at a first side of the second wafer. The comb lines provide an indication of an alignment of the first wafer and second wafer by a number or arrangement of connections made by the plurality of comb lines between the test node lines and the common node.

Abstract: The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having via sidewall surfaces defined by a semiconductor substrate. The via sidewall surfaces have a first portion and a second portion. A conductive layer is disposed in the via on the first portion of the via sidewall surfaces, and a dielectric layer is disposed on the second portion of the via sidewall surfaces. The dielectric layer is disposed between the second portion of the via sidewall surfaces and the conductive layer. In an example, the dielectric layer is an oxide layer.

Abstract: A micro electromechanical system (MEMS) device includes a MEMS section attached to a substrate, and a cap bonded to a first surface of the substrate. The MEMS device further includes a carrier bonded to a second surface of the substrate opposite the first surface, wherein the carrier is free of active devices, and the cap and the carrier define a vacuum region surrounding the MEMS section. The MEMS device further includes a bond pad on a surface of the carrier opposite the MEMS section, wherein the bond pad is electrically connected to the MEMS section.

Abstract: A method includes forming a MEMS device, forming a bond layer adjacent the MEMS device, and forming a protection layer over the bond layer. The steps of forming the bond layer and the protection layer include in-situ deposition of the bond layer and the protection layer.

Abstract: A wafer grinding system includes a robot arm having a suction board at one end and a table within reach of the robot arm. An upper surface of the table has a vacuum surface for sucking and holding wafers. A pusher coupled to the robot arm extends about the periphery of the suction board. The pusher flattens wafers against the upper surface of the table, allowing the table to hold by suction wafers that would otherwise be too bowed to be held in that way. Additionally, a table can have a vacuum area that is small in comparison to the wafers, which is another way of increasing the magnitude of wafer bow that can be tolerated. A grinding system can use the reduced vacuum area concept to allow the positioning table to hold bowed wafers and the pusher concept to allow the chuck tables to hold bowed wafers.

Abstract: Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.

Abstract: Provided is a composite diaphragm which includes a base layer and at least a graphyne including layer. The base layer has a central portion and a peripheral portion disposed at the periphery of the central portion. The graphyne including layer is disposed on the surface of the base layer. As graphyne is a lightweight and highly rigid material with a two-dimensional structure, composite diaphragms made of graphyne manifest characteristics, such as high stiffness, high toughness and low density, and thus achieve high practicability, such as high durability and high capability of producing high-definition tone.

Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.

Abstract: The present disclosure relates to a method of gettering that provides for a high efficiency gettering process by depositing a gettering material on a roughened substrate surface, and an associated apparatus. In some embodiments, the method is performed by providing a substrate into a processing chamber having residual gases. One or more cavities are formed in the substrate at locations between bonding areas on a top surface of the substrate. Respective cavities have roughened interior surfaces that vary in a plurality of directions. A getter layer is deposited into the one or more cavities. The roughened interior surfaces of the one or more cavities enable the substrate to more effectively absorb the residual gases, thereby increasing the efficiency of the gettering process.

Abstract: A semiconductor structure includes a molding compound, a conductive plug, and a cover. The conductive plug is in the molding compound. The cover is over a top meeting joint between the conductive plug and the molding compound. The semiconductor structure further has a dielectric. The dielectric is on the cover and the molding compound.

Abstract: An embodiment low contamination chamber includes a gas inlet, an adjustable top electrode, an adjustable bottom electrode, and an outlet. The chamber is configured to adjust a distance between the adjustable top and bottom electrodes in accordance with a desired density of plasma disposed between the top electrode and the bottom electrode.

Abstract: Alignment systems, and wafer bonding alignment systems and methods are disclosed. In some embodiments, an alignment system for a wafer bonding system includes means for monitoring an alignment of a first wafer and a second wafer, and means for adjusting a position of the second wafer. The alignment system includes means for feeding back a relative position of the first wafer and the second wafer to the means for adjusting the position of the second wafer before and during a bonding process for the first wafer and the second wafer.