Patents by Inventor Lan Lin

Lan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Low Contamination Chamber for Surface Activation
    Publication number: 20160181073
    Abstract: An embodiment low contamination chamber includes a gas inlet, an adjustable top electrode, and an adjustable bottom electrode. The low contamination chamber is configured to adjust a distance between the adjustable top electrode and the adjustable bottom electrode in response to a desired density of plasma and a measured density of plasma measured between the adjustable top electrode and the adjustable bottom electrode during a surface activation process. The low contamination chamber further includes an outlet.
    Type: Application
    Filed: February 26, 2016
    Publication date: June 23, 2016
    Inventors: Ping-Yin Liu, Xin-Hua Huang, Lee-Chuan Tseng, Lan-Lin Chao
  • Air Trench in Packages Incorporating Hybrid Bonding
    Publication number: 20160163684
    Abstract: A package component includes a surface dielectric layer including a planar top surface, a metal pad in the surface dielectric layer and including a second planar top surface level with the planar top surface, and an air trench on a side of the metal pad. The sidewall of the metal pad is exposed to the air trench.
    Type: Application
    Filed: February 12, 2016
    Publication date: June 9, 2016
    Inventors: Bruce C.S. Chou, Chen-Jong Wang, Ping-Yin Liu, Jung-Kuo Tu, Tsung-Te Chou, Xin-Hua Huang, Hsun-Chung Kuang, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • 3D Integrated Circuit and Methods of Forming the Same
    Publication number: 20160155665
    Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.
    Type: Application
    Filed: February 8, 2016
    Publication date: June 2, 2016
    Inventors: Hsun-Chung Kuang, Yen-Chang Chu, Cheng-Tai Hsiao, Ping-Yin Liu, Lan-Lin Chao, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
  • Transfer module for bowed wafers
    Patent number: 9355882
    Abstract: A wafer grinding system includes a robot arm having a suction board at one end and a table within reach of the robot arm. An upper surface of the table has a vacuum surface for sucking and holding wafers. A pusher coupled to the robot arm extends about the periphery of the suction board. The pusher flattens wafers against the upper surface of the table, allowing the table to hold by suction wafers that would otherwise be too bowed to be held in that way. Additionally, a table can have a vacuum area that is small in comparison to the wafers, which is another way of increasing the magnitude of wafer bow that can be tolerated. A grinding system can use the reduced vacuum area concept to allow the positioning table to hold bowed wafers and the pusher concept to allow the chuck tables to hold bowed wafers.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: May 31, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Tung Wu, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai
  • Hermetic wafer level packaging
    Patent number: 9337168
    Abstract: Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum-based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: May 10, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Richard Chu, Martin Liu, Chia-Hua Chu, Yuan-Chih Hsieh, Chung-Hsien Lin, Lan-Lin Chao, Chun-Wen Cheng, Mingo Liu
  • Hybrid bonding and apparatus for performing the same
    Patent number: 9331032
    Abstract: A method includes performing a hybrid bonding to bond a first package component to a second package component, so that a bonded pair is formed. In the bonded pair, first metal pads in the first package component are bonded to second metal pads in the second package component, and a first surface dielectric layer at a surface of the first package component is bonded to a second surface dielectric layer at a surface of the second package component. After the hybrid bonding, a thermal compressive annealing is performed on the bonded pair.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: May 3, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Yin Liu, Xin-Hua Huang, Chih-Hui Huang, Lan-Lin Chao, Yeur-Luen Tu, Yan-Chih Lu, Jhy-Jyi Sze, Chia-Shiung Tsai
  • Debonding Schemes
    Publication number: 20160111316
    Abstract: A method includes receiving a wafer stack having at least two wafers bonded together. At least one blade is inserted between a first wafer of the at least two wafers and a second wafer of the at least two wafers. The blade has a channel configured to inject air or fluid. The first wafer is debonded from the second wafer using the at least one blade. In another embodiment, a detacher having a convex bottom surface is attached to the wafer stack. The first wafer is debonded from the second wafer using the detacher.
    Type: Application
    Filed: October 17, 2014
    Publication date: April 21, 2016
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Lan-Lin Chao, Chia-Shiung Tsai
  • METHOD OF IMPROVING GETTER EFFICIENCY BY INCREASING SUPERFICIAL AREA
    Publication number: 20160101976
    Abstract: In some embodiments, the present disclosure relates to a MEMs (micro-electromechanical system) package device having a getter layer. The MEMs package includes a first substrate having a cavity located within an upper surface of the first substrate. The cavity has roughened interior surfaces. A getter layer is arranged onto the roughened interior surfaces of the cavity. A bonding layer is arranged on the upper surface of the first substrate on opposing sides of the cavity, and a second substrate bonded to the first substrate by the bonding layer. The second substrate is arranged over the cavity. The roughened interior surfaces of the cavity enables more effective absorption of residual gases, thereby increasing the efficiency of a gettering process.
    Type: Application
    Filed: December 14, 2015
    Publication date: April 14, 2016
    Inventors: Yuan-Chih Hsieh, Li-Cheng Chu, Hung-Hua Lin, Chih-Jen Chan, Lan-Lin Chao
  • Electric vehicle battery exchanging system for reuse applications
    Patent number: 9302592
    Abstract: An electrical battery exchanging system for reuse application is disclosed. The system includes: a number of rechargeable battery packs, a battery condition detecting module, a user ID checking module, a power source, a charging controlling module. Since the system can monitor conditions of rechargeable battery cells of the rechargeable battery packs and uses user ID for operating control purpose, it has benefits of conveniently exchanging low-power battery with fully charged one, easily sorting out end-of-life batteries and getting them for recycle or reuse, simply charging service fee and stably operating under a business model.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: April 5, 2016
    Assignee: Go-Tech Energy Co. Ltd.
    Inventors: Hung-Lan Lin, Li-Zen Lai
  • MANUFACTURING METHOD FOR STIFFENED DIAPHRAGM AND THE MANUFACTURED DIAPHRAGM USING SAME
    Publication number: 20160088394
    Abstract: A stiffened diaphragm manufacturing method and the manufactured diaphragm using same are provided. The manufacturing method includes the steps of: applying a hot glue layer to a side of a stiffened plate; putting a base layer on the hot glue layer, and then heating and adhering the base layer and the stiffened plate together; and performing a pressing process on the base layer and the stiffened plate to form a diaphragm having a central portion and a surround portion. The stiffened plate is coated uniformly with the hot glue layer and then put on the base layer to undergo heating and adhesion; hence, an oversupply or undersupply of a glue will be unlikely to happen. Furthermore, the manufacturing process is simple and attains high-strength adhesion between the stiffened plate and the base layer.
    Type: Application
    Filed: September 19, 2014
    Publication date: March 24, 2016
    Inventors: Chen-Mao YANG, Ching-Lan LIN, Po-Yu CHEN, Yi-Lin HSIEH, Feng-Min LAI
  • Low contamination chamber for surface activation
    Patent number: 9293303
    Abstract: An embodiment low contamination chamber includes a gas inlet, an adjustable top electrode, an adjustable bottom electrode, and an outlet. The chamber is configured to adjust a distance between the adjustable top and bottom electrodes in accordance with a desired density of plasma disposed between the top electrode and the bottom electrode.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: March 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Yin Liu, Xin-Hua Huang, Lee-Chuan Tseng, Lan-Lin Chao
  • Wafer level packaging bond
    Patent number: 9293445
    Abstract: A device is described in one embodiment that includes a micro-electro-mechanical systems (MEMS) device disposed on a first substrate and a semiconductor device disposed on a second substrate. A bond electrically connects the MEMS device and the semiconductor device. The bond includes an interface between a first bonding layer including silicon on the first substrate and a second bonding layer including aluminum on the second substrate. The physical interface between the aluminum and silicon (e.g., amorphous silicon) can provide an electrical connection.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: March 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Yin Liu, Li-Chen Chu, Hung-Hua Lin, H. T. Huang, Jung-Huei Peng, Yuan-Chih Hsieh, Lan-Lin, Chun-Wen Cheng, Chia-Shiung Tsai
  • POWER SYSTEM EQUIPMENT DESIGN FLAW IDENTIFICATION
    Publication number: 20160041552
    Abstract: Among other things, one or more techniques and/or systems are provided for providing recommendations to address design flaws of power system equipment and/or model design flaws for equipment model types of power system equipment. For example, historical sensor data and/or historical field test data, collected from power system equipment, may be analyzed to identify a design flaw of the power system equipment (e.g., a design flaw of a seal ring). A redesign cost to redesign the power system equipment, a failure impact of a failure from the design flaw, a maintenance repair and/or replacement cost, a manufacture alternative component cost to use an alternative component for manufacturing the power system equipment, and/or other factors may be taken into account to crate and provide a recommendation to address the design flaw.
    Type: Application
    Filed: October 19, 2015
    Publication date: February 11, 2016
    Inventors: Aldo Dagnino, Luiz V. Cheim, Lan Lin, Poorvi Patel, Asim Fazlagic
  • 3D integrated circuit and methods of forming the same
    Patent number: 9257399
    Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: February 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsun-Chung Kuang, Yen-Chang Chu, Cheng-Tai Hsiao, Ping-Yin Liu, Lan-Lin Chao, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
  • Method, device and storage medium for processing virus
    Patent number: 9251344
    Abstract: The present disclosure relates to a method, a device and a storage medium for processing virus which can automatically distinguish which of processing mode is best for the current status of the electronic apparatus. The method includes: detecting a virus scan operation; in response to the virus scan operation, determining whether conditions (i) and (ii) are true, wherein the condition (i) is true when a time interval between a last time of processing virus using a first virus processing mode and the current time is larger than a preset interval, the condition (ii) is true when at least one of risk situations exist during a time period between the last time of processing virus using the first virus processing mode and the current time; if one of conditions (i) and (ii) being true, calling the first virus processing mode to scan files in the electronic apparatus.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: February 2, 2016
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Ye Zou, Ru-Lan Lin, Wen-Liang Tang
  • Method of improving getter efficiency by increasing superficial area
    Patent number: 9242853
    Abstract: The present disclosure relates to a method of gettering that provides for a high efficiency gettering process by depositing a gettering material on a roughened substrate surface, and an associated apparatus. In some embodiments, the method is performed by providing a substrate into a processing chamber having residual gases. One or more cavities are formed in the substrate at locations between bonding areas on a top surface of the substrate. Respective cavities have roughened interior surfaces that vary in a plurality of directions. A getter layer is deposited into the one or more cavities. The roughened interior surfaces of the one or more cavities enable the substrate to more effectively absorb the residual gases, thereby increasing the efficiency of the gettering process.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: January 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yuan-Chih Hsieh, Li-Cheng Chu, Hung-Hua Lin, Chih-Jen Chan, Lan-Lin Chao
  • PROFILING TRANSFORMER OF POWER SYSTEM
    Publication number: 20160005522
    Abstract: Method and system for predicting an oil temperature of a transformer for a desired load and/or predicting a load that a transformer can support for a desired time. A machine learning algorithm is developed using historical data of a transformer. After the algorithm is developed, historical data corresponding to the transformer are input into the algorithm to develop a profile of the transformer describing how the temperature of oil within the transformer is expected to change as a function of a desired load. Using the profile, the of temperature of the transformer is predicted for a desired load. In this way, a prediction is made as to whether and/or for how long a transformer may support a desired load before the oil temperature reaches a specified threshold and/or before the transformer fails due to the load.
    Type: Application
    Filed: November 19, 2013
    Publication date: January 7, 2016
    Inventors: Aldo DAGNINO, Luiz CHEIM, Lan LIN, Poorvi PATEL
  • ELECTRIC VEHICLE BATTERY EXCHANGING SYSTEM FOR REUSE APPLICATIONS
    Publication number: 20150367743
    Abstract: An electrical battery exchanging system for reuse application is disclosed. The system includes: a number of rechargeable battery packs, a battery condition detecting module, a user ID checking module, a power source, a charging controlling module. Since the system can monitor conditions of rechargeable battery cells of the rechargeable battery packs and uses user ID for operating control purpose, it has benefits of conveniently exchanging low-power battery with fully charged one, easily sorting out end-of-life batteries and getting them for recycle or reuse, simply charging service fee and stably operating under a business model.
    Type: Application
    Filed: June 18, 2014
    Publication date: December 24, 2015
    Inventors: Hung-Lan LIN, Li-Zen LAI
  • HYBRID BONDING MECHANISMS FOR SEMICONDUCTOR WAFERS
    Publication number: 20150357296
    Abstract: A method of forming a hybrid bonding structure includes depositing an etch stop layer over surface of a substrate, wherein the substrate comprises a conductive structure, and the etch stop layer contacts the conductive structure. The method further includes depositing a dielectric material over the etch stop layer. The method further includes depositing a first diffusion barrier layer over the dielectric material. The method further includes forming an opening extending through the etch stop layer, the dielectric material and the diffusion barrier layer. The method further includes lining the opening with a second diffusion barrier layer. The method further includes depositing a conductive pad on the second diffusion barrier layer in the opening, wherein a surface of the first diffusion barrier layer is aligned with a surface of the conductive pad.
    Type: Application
    Filed: August 20, 2015
    Publication date: December 10, 2015
    Inventors: Ping-Yin LIU, Szu-Ying CHEN, Chen-Jong WANG, Chih-Hui HUANG, Xin-Hua HUANG, Lan-Lin CHAO, Yeur-Luen TU, Chia-Shiung TSAI, Xiaomeng CHEN
  • Apparatus and Method for Wafer Level Bonding
    Publication number: 20150357226
    Abstract: A system for and a method of bonding a first wafer to a second wafer are provided. A second wafer chuck has a second surface, a profile of the second surface being adjustable by a profile control layer. The first wafer is placed on a first surface of a first wafer chuck, and the second wafer is placed on the second surface of the second wafer chuck. The first wafer and the second wafer are warped prior to bonding to form a first warped wafer and a second warped wafer, respectively. The first warped wafer is bonded to the second warped wafer.
    Type: Application
    Filed: June 6, 2014
    Publication date: December 10, 2015
    Inventors: Ping-Yin Liu, Yen-Chang Chu, Xin-Hua Huang, Lan-Lin Chao, Yeur-Luen Tu, Ru-Liang Lee