Patents by Inventor Lan Lin

Lan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • HYBRID BONDING MECHANISMS FOR SEMICONDUCTOR WAFERS
    Publication number: 20140117546
    Abstract: The embodiments of diffusion barrier layer described above provide mechanisms for forming a copper diffusion barrier layer to prevent device degradation for hybrid bonding of wafers. The diffusion barrier layer(s) encircles the copper-containing conductive pads used for hybrid bonding. The diffusion barrier layer can be on one of the two bonding wafers or on both bonding wafers.
    Type: Application
    Filed: October 31, 2012
    Publication date: May 1, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ping-Yin LIU, Szu-Ying CHEN, Chen-Jong WANG, Chih-Hui HUANG, Xin-Hua HUANG, Lan-Lin CHAO, Yeur-Luen TU, Chia-Chiung TSAI, Xiaomeng CHEN
  • Apparatus for Vertically Integrated Backside Illuminated Image Sensors
    Publication number: 20140113398
    Abstract: A backside illuminated image sensor comprises a photodiode and a first transistor located in a first chip, wherein the first transistor is electrically coupled to the photodiode. The backside illuminated image sensor further comprises a second transistor formed in a second chip and a plurality of logic circuits formed in a third chip, wherein the second chip is stacked on the first chip and the third chip is stacked on the second chip. The logic circuit, the second transistor and the first transistor are coupled to each other through a plurality of boding pads and through vias.
    Type: Application
    Filed: December 20, 2013
    Publication date: April 24, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Jui Wang, Szu-Ying Chen, Jen-Cheng Liu, Dun-Nian Yaung, Ping-Yin Liu, Lan-Lin Chao
  • METHOD AND DEVICE FOR INTERFACE DISPLAY
    Publication number: 20140089842
    Abstract: The present disclosure relates to an interface display method, the method comprising: generating a first screen interface and a second screen interface, wherein the first screen interface displays a functional interface associated with an application, and the second screen interface displays a navigation interface comprising functional modules associated with the application; displaying the first screen interface; displaying the second screen interface when the second screen interface is triggered; and displaying an interface associated with a functional module in the first screen interface when the functional module is selected from the second screen interface. This interface display method accomplishes convenient switching between functional modules without occupying screen display space. The present disclosure also provides an interface display device.
    Type: Application
    Filed: November 26, 2013
    Publication date: March 27, 2014
    Applicant: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Ru Lan LIN, Can Cai YUAN, Sen Sheng XU, Hai Feng DING, Zi Hao CEN, Jia En LIU
  • METHOD AND MOBILE TERMINAL FOR ENHANCING THE SECURITY OF A MOBILE TERMINAL
    Publication number: 20140059669
    Abstract: The present disclosure discloses a method and mobile terminal for enhancing mobile terminal security, and relates to the information security field. The method includes: a mobile terminal providing in advance a target list to a user, setting at least one user-selected target from the list to a hidden state, and storing a password for a protected space set by the user, monitoring a specified application for the user to enter the password for the protected space, when detecting the user entering the password for the protected space via the specified application, entering the protected space, and restoring the target from a hidden state to a visible state, wherein the target can be an application/file at the mobile terminal. The mobile terminal can include: a setting module and a controlling module. The present disclosure can greatly enhance the security of the applications/documents at the mobile terminal.
    Type: Application
    Filed: September 30, 2013
    Publication date: February 27, 2014
    Applicant: Tencent Technology (Shenzhen) Company Limited
    Inventors: Can Cai YUAN, Sen Sheng XU, Ru Lan LIN, Lei LONG
  • Semiconductor Having a High Aspect Ratio Via
    Publication number: 20140054779
    Abstract: The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having via sidewall surfaces defined by a semiconductor substrate. The via sidewall surfaces have a first portion and a second portion. A conductive layer is disposed in the via on the first portion of the via sidewall surfaces, and a dielectric layer is disposed on the second portion of the via sidewall surfaces. The dielectric layer is disposed between the second portion of the via sidewall surfaces and the conductive layer. In an example, the dielectric layer is an oxide layer.
    Type: Application
    Filed: November 6, 2013
    Publication date: February 27, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yuan-Chih Hsieh, Li-Cheng Chu, Ming-Tung Wu, Ping-Yin Liu, Lan-Lin Chao, Chia-Shiung Tsai
  • GRINDING WHEEL FOR WAFER EDGE TRIMMING
    Publication number: 20140051336
    Abstract: A grinding wheel for wafer edge trimming includes a head having an open side and an abrasive end bonded around an edge of the open side of the head. The abrasive end is arranged to have multiple simultaneous contacts around a wafer edge during the wafer edge trimming.
    Type: Application
    Filed: September 28, 2012
    Publication date: February 20, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Xin-Hua HUANG, Ping-Yin LIU, Yuan-Chih HSIEH, Lan-Lin CHAO, Chia-Shiung TSAI
  • Hermetic wafer level packaging
    Patent number: 8648468
    Abstract: Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum -based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: February 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Richard Chu, Martin Liu, Chia-Hua Chu, Yuan-Chih Hsieh, Chung-Hsien Lin, Lan-Lin Chao, Chun-Wen Cheng, Mingo Liu
  • Wafer level packaging bond
    Patent number: 8647962
    Abstract: The present disclosure provides a method of bonding a plurality of substrates. In an embodiment, a first substrate includes a first bonding layer. The second substrate includes a second bonding layer. The first bonding layer includes silicon; the second bonding layer includes aluminum. The first substrate and the second substrate are bonded forming a bond region having an interface between the first bonding layer and the second bonding layer. A device having a bonding region between substrates is also provided. The bonding region includes an interface between a layer including silicon and a layer including aluminum.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: February 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Martin Liu, Richard Chu, Hung Hua Lin, Hsin-Ting Huang, Jung-Huei Peng, Yuan-Chih Hsieh, Lan-Lin Chao, Chun-Wen Cheng, Chia-Shiung Tsai
  • Systems and Methods of Separating Bonded Wafers
    Publication number: 20140020818
    Abstract: Systems and methods of separating bonded wafers are disclosed. In one embodiment, a system for separating bonded wafers includes a support for the bonded wafers and means for applying a sheer force to the bonded wafers. The system also includes means for applying a vacuum to the bonded wafers.
    Type: Application
    Filed: July 20, 2012
    Publication date: January 23, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai
  • Apparatus for vertically integrated backside illuminated image sensors
    Patent number: 8629524
    Abstract: A backside illuminated image sensor comprises a photodiode and a first transistor located in a first chip, wherein the first transistor is electrically coupled to the photodiode. The backside illuminated image sensor further comprises a second transistor formed in a second chip and a plurality of logic circuits formed in a third chip, wherein the second chip is stacked on the first chip and the third chip is stacked on the second chip. The logic circuit, the second transistor and the first transistor are coupled to each other through a plurality of boding pads and through vias.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Jui Wang, Szu-Ying Chen, Jen-Cheng Liu, Dun-Nian Yaung, Ping-Yin Liu, Lan-Lin Chao
  • Hybrid Bonding Systems and Methods for Semiconductor Wafers
    Publication number: 20140011324
    Abstract: Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.
    Type: Application
    Filed: July 5, 2012
    Publication date: January 9, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ping-Yin Liu, Shih-Wei Lin, Xin-Hua Huang, Lan-Lin Chao, Chia-Shiung Tsai
  • Apparatus and Method for Backside Illuminated Image Sensors
    Publication number: 20130334638
    Abstract: A backside illuminated image sensor comprises a photodiode and a first transistor located in a first substrate, wherein the first transistor is electrically coupled to the photodiode. The backside illuminated image sensor further comprises a plurality of logic circuits formed in a second substrate, wherein the second substrate is stacked on the first substrate and the logic circuit are coupled to the first transistor through a plurality of bonding pads.
    Type: Application
    Filed: June 15, 2012
    Publication date: December 19, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Ying Chen, Tzu-Jui Wang, Jen-Cheng Liu, Dun-Nian Yaung, Ping-Yin Liu, Lan-Lin Chao
  • Three Dimensional Integrated Circuit Structures and Hybrid Bonding Methods for Semiconductor Wafers
    Publication number: 20130320556
    Abstract: Three dimensional integrated circuit (3DIC) structures and hybrid bonding methods for semiconductor wafers are disclosed. A 3DIC structure includes a first semiconductor device having first conductive pads disposed within a first insulating material on a top surface thereof, the first conductive pads having a first recess on a top surface thereof. The 3DIC structure includes a second semiconductor device having second conductive pads disposed within a second insulating material on a top surface thereof coupled to the first semiconductor device, the second conductive pads having a second recess on a top surface thereof. A sealing layer is disposed between the first conductive pads and the second conductive pads in the first recess and the second recess. The sealing layer bonds the first conductive pads to the second conductive pads. The first insulating material is bonded to the second insulating material.
    Type: Application
    Filed: June 5, 2012
    Publication date: December 5, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ping-Yin Liu, Xin-Hua Huang, Lan-Lin Chao, Chia-Shiung Tsai
  • Semiconductor having a high aspect ratio via
    Patent number: 8598687
    Abstract: The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having via sidewall surfaces defined by a semiconductor substrate. The via sidewall surfaces have a first portion and a second portion. A conductive layer is disposed in the via on the first portion of the via sidewall surfaces, and a dielectric layer is disposed on the second portion of the via sidewall surfaces. The dielectric layer is disposed between the second portion of the via sidewall surfaces and the conductive layer. In an example, the dielectric layer is an oxide layer.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: December 3, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yuan-Chih Hsieh, Richard Chu, Ming-Tung Wu, Martin Liu, Lan-Lin Chao, Chia-Shiung Tsai
  • Apparatus for Vertically Integrated Backside Illuminated Image Sensors
    Publication number: 20130285180
    Abstract: A backside illuminated image sensor comprises a photodiode and a first transistor located in a first chip, wherein the first transistor is electrically coupled to the photodiode. The backside illuminated image sensor further comprises a second transistor formed in a second chip and a plurality of logic circuits formed in a third chip, wherein the second chip is stacked on the first chip and the third chip is stacked on the second chip. The logic circuit, the second transistor and the first transistor are coupled to each other through a plurality of boding pads and through vias.
    Type: Application
    Filed: April 27, 2012
    Publication date: October 31, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Jui Wang, Szu-Ying Chen, Jen-Cheng Liu, Dun-Nian Yaung, Ping-Yin Liu, Lan-Lin Chao
  • Method and Apparatus for Image Sensor Packaging
    Publication number: 20130284885
    Abstract: Methods and apparatus for packaging a backside illuminated (BSI) image sensor or a sensor device with an application specific integrated circuit (ASIC) are disclosed. According to an embodiment, a sensor device may be bonded together face-to-face with an ASIC without using a carrier wafer, where corresponding bond pads of the sensor are aligned with bond pads of the ASIC and bonded together, in a one-to-one fashion. A column of pixels of the sensor may share a bond bad connected by a shared inter-metal line. The bond pads may be of different sizes and configured in different rows to be disjoint from each other. Additional dummy pads may be added to increase the bonding between the sensor and the ASIC.
    Type: Application
    Filed: April 27, 2012
    Publication date: October 31, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Szu-Ying Chen, Ping-Yin Liu, Calvin Yi-Ping Chao, Tzu-Jui Wang, Jen-Cheng Liu, Dun-Nian Yaung, Lan-Lin Chao
  • BIOLOGICAL SENSING STRUCTURES AND METHODS OF FORMING THE SAME
    Publication number: 20130208371
    Abstract: A method of forming of biological sensing structures including a portion of a substrate is recessed to form a plurality of mesas in the substrate. Each of the plurality of mesas has a top surface and a sidewall surface. A first light reflecting layer is deposited over the top surface and the sidewall surface of each mesa. A filling material is formed over a first portion of the first light reflecting layer. A stop layer is deposited over the filling material and a second portion of the first light reflecting layer. A sacrificial layer is formed over the stop layer and is planarized exposing the stop layer. A first opening is formed in the stop layer and the first light reflecting layer. A second light reflecting layer is deposited over the first opening. A second opening is formed in the second light reflecting layer.
    Type: Application
    Filed: February 13, 2012
    Publication date: August 15, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Hua LIN, Li-Cheng CHU, Ming-Tung WU, Yuan-Chih HSIEH, Lan-Lin CHAO, Chia-Shiung TSAI
  • Methods of Bonding Caps for MEMS Devices
    Publication number: 20130203199
    Abstract: A method includes bonding a first bond layer to a second bond layer through eutectic bonding. The step of bonding includes heating the first bond layer and the second bond layer to a temperature higher than a eutectic temperature of the first bond layer and the second bond layer, and performing a pumping cycle. The pumping cycle includes applying a first force to press the first bond layer and the second bond layer against each other. After the step of applying the first force, a second force lower than the first force is applied to press the first bond layer and the second bond layer against each other. After the step of applying the second force, a third force higher than the second force is applied to press the first bond layer and the second bond layer against each other.
    Type: Application
    Filed: February 2, 2012
    Publication date: August 8, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Li-Cheng Chu, Yuan-Chih Hsieh, Lan-Lin Chao, Chun-Wen Cheng, Chia-Shiung Tsai
  • Semiconductor having a high aspect ratio via
    Patent number: 8445380
    Abstract: The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a method for forming a via structure includes forming a via in a semiconductor substrate, wherein via sidewalls of the via are defined by the semiconductor substrate; forming a dielectric layer on the via sidewalls; removing the dielectric layer from a portion of the via sidewalls; and forming a conductive layer to fill the via, wherein the conductive layer is disposed over the dielectric layer and the portion of the via sidewalls. In an example, the dielectric layer is an oxide layer.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: May 21, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yuan-Chih Hsieh, Richard Chu, Ming-Tung Wu, Martin Liu, Lan-Lin Chao, Chia-Shiung Tsai
  • BACKLIGHT MODULE
    Publication number: 20130121025
    Abstract: A backlight module includes a light guide plate and a light emitting unit. The light guide plate has a first side surface, a second side surface, and a third side surface. The first side surface is located opposite to the second side surface. A height of the first side surface is greater than a height of the second side surface. The third side surface is located between the first side surface and the second side surface and has a light entrance surface and a light exit surface. The light entrance surface is connected to the first side surface and the light exit surface. The light exit surface is connected to the second side surface. An included angle is formed between the light entrance surface and the light exit surface. The light emitting unit is disposed on the light entrance surface.
    Type: Application
    Filed: April 18, 2012
    Publication date: May 16, 2013
    Inventors: Ya-Lan Lin, Ching-Feng Chen, Cheng-Min Tsai, Ming-Sheng Lai, Ren-Wei Huang