Abstract: A method for laying out process dummy cells in relationship to inside memory cells of a memory array includes (a) calculating an initial process performance parameter for the memory array; (b) changing dummy cell layout configuration for a layer electrically connected to inside cells; (c) applying lithographic simulation and yield model for both the inside memory cells and the changed layout configuration process dummy cells; and (d) repeating steps (b) and (c) until yield is maximized. Checks may be performed to ensure that there is enough room to make the change and that there is no significant adverse effect to neighboring circuits. The process performance parameter may be yield or a process window for the inside memory cells.

Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

Abstract: A method of designing a mask for projecting an image of an integrated circuit design in lithographic processing, wherein the integrated circuit layout has a plurality of segments of critical width. The method comprises creating a first mask design by aligning mask features used to assist in projecting critical width segments with the critical width segments of the integrated circuit design, such that the first mask design meets predetermined manufacturability design rules, and creating a second mask design by aligning mask features with the critical width segments of the integrated circuit design, such that the second mask design meets predetermined lithographic design rules in regions local to the critical width segments.

Abstract: A mechanism is provided for converting a set of single-layer design rules into a set of split-layer design rules for double patterning lithography (DPL). The set of single-layer design rules and minimum lithographic resolution pitch constraints for single exposure are identified. The set of single-layer design rules comprise a first plurality of minimum distances that are required by a set of first shapes in a single-layer design. Each of the first plurality of minimum distances in the set of single-layer design rules are modified with regard to the minimum lithographic resolution pitch constraints for single exposure, thereby forming the set of split-layer design rules. The set of split-layer design rules comprise a second plurality of minimum distances that are required by a set of second shapes and a set of third shapes in a split-layer design. The set of split-layer design rules are then coded into a design rule checker.

Abstract: A method of automatic calibration of a design for manufacturing (DfM) simulation tool includes providing, as a first input, one or more defined rules for each of one or more semiconductor device levels to be simulated by the tool, and providing, as a second input, a plurality of defined feature size threshold ranges and increments for use in histogram generation of a number of failures with respect to a reference circuit; providing, as a third input, the reference circuit; executing the defined rules for the semiconductor device levels to be simulated, and outputting a fail count for the reference circuit at each defined threshold value, thereby generating histogram data of fail count versus threshold for the reference circuit; and providing, as a fourth input, a defined fail count metric, thereby calibrating the DfM tool for use with respect to a target circuit.

Abstract: A contour of a mask design for an integrated circuit is modified to compensate for systematic variations arising from non-optical effects such as stress, well proximity, rapid thermal anneal, or spacer thickness. Electrical characteristics of a simulated integrated circuit chip fabricated using the mask design are extracted and compared to design specifications, and one or more edges of the contour are adjusted to reduce the systematic variation until the electrical characteristic is within specification. The particular electrical characteristic preferably depends on which layer is to be fabricated from the mask: on-current for a polysilicon; resistance for contact; resistance and capacitance for metal; current for active; and resistance for vias. For systematic threshold voltage variation, the contour is adjusted to match a gate length which corresponds to an on-current value according to pre-calculated curves for contour current and gate length at a nominal threshold voltage of the chip.

Abstract: The present invention provides a method and computer program product for designing an on-wafer target for use by a model-based design tool such as OPC or OPC verification. The on-wafer target is modified by modifying a critical dimension so as to improve or optimize an electrical characteristic, while also ensuring that one or more yield constraints are satisfied. The use of an electrically optimized target can result in cost-effective mask designs that better meet the designers' intent.

Abstract: A method of automatic calibration of a design for manufacturing (DfM) simulation tool includes providing, as a first input, one or more defined rules for each of one or more semiconductor device levels to be simulated by the tool, and providing, as a second input, a plurality of defined feature size threshold ranges and increments for use in histogram generation of a number of failures with respect to a reference circuit; providing, as a third input, the reference circuit; executing the defined rules for the semiconductor device levels to be simulated, and outputting a fail count for the reference circuit at each defined threshold value, thereby generating histogram data of fail count versus threshold for the reference circuit; and providing, as a fourth input, a defined fail count metric, thereby calibrating the DfM tool for use with respect to a target circuit.

Abstract: An approach that provides electrically driven optical proximity correction is described. In one embodiment, there is a method for performing an electrically driven optical proximity correction. In this embodiment, an integrated circuit mask layout representative of a plurality of layered shapes each defined by features and edges is received. A lithography simulation is run on the mask layout. An electrical characteristic is extracted from the output of the lithography simulation for each layer of the mask layout. A determination as to whether the extracted electrical characteristic is in conformance with a target electrical characteristic is made. Edges of the plurality of layered shapes in the mask layout are adjusted in response to determining that the extracted electrical characteristic for a layer in the mask layout fails to conform with the target electrical characteristic.

Abstract: A method, and computer program product and system for performing the method, is provided for designing a mask used in the manufacture of semiconductor integrated circuits, in which a model of the lithographic process is used during the mask design process. More particularly, the on-wafer process model is a function of optical image parameters that are calibrated using measurements from a test pattern. An uncertainty metric for the predicted response simulated by the on-wafer process model is computed for a given evaluation point of interest as a function of a distance metric between the collective optical image parameters simulated at the given evaluation point and the collective optical image parameters at the calibration data points. The uncertainty metric preferably is also a function of the sensitivity of the on-wafer process model response to changes in the optical image parameters.

Abstract: A contour of a mask design for an integrated circuit is modified to compensate for systematic variations arising from non-optical effects such as stress, well proximity, rapid thermal anneal, or spacer thickness. Electrical characteristics of a simulated integrated circuit chip fabricated using the mask design are extracted and compared to design specifications, and one or more edges of the contour are adjusted to reduce the systematic variation until the electrical characteristic is within specification. The particular electrical characteristic preferably depends on which layer is to be fabricated from the mask: on-current for a polysilicon; resistance for contact; resistance and capacitance for metal; current for active; and resistance for vias. For systematic threshold voltage variation, the contour is adjusted to match a gate length which corresponds to an on-current value according to pre-calculated curves for contour current and gate length at a nominal threshold voltage of the chip.

Abstract: A method of designing an alternating phase shifting mask for projecting an image of an integrated circuit design. Phase units are binary colorable within each unit of the hierarchical circuit design, e.g., cell, an array, a net, or array of nets and/or cells, the phase shapes. The assignment of phases or colors within a hierarchical unit will be correctly binary colored to satisfy the lithographic, manufacturability and other design rules, referred to collectively as coloring rules. During assembly with other units, the coloring of phases in a hierarchical unit may change (e.g., be reversed or flipped), but the correct binary colorability of a hierarchical unit is preserved, which simplifies assembly of the integrated circuit layout.

Abstract: A method of designing a mask for projecting an image of an integrated circuit design in lithographic processing, wherein the integrated circuit layout has a plurality of segments of critical width. The method comprises creating a first mask design by aligning mask features used to assist in projecting critical width segments with the critical width segments of the integrated circuit design, such that the first mask design meets predetermined manufacturability design rules, and creating a second mask design by aligning mask features with the critical width segments of the integrated circuit design, such that the second mask design meets predetermined lithographic design rules in regions local to the critical width segments.

Abstract: A method for designing a mask for fabricating an integrated circuit is provided wherein a mask layout that requires coloring, such as for alternating phase shift, double-exposure and double-exposure-etch masks, is organized into uncolored hierarchical design units. Prior to modification by OPC, each hierarchical design unit is locally colored. OPC is then performed on the locally colored hierarchical design unit. The local coloring information for the hierarchically arranged OPC-modified design unit may be discarded. After OPC modification, the uncolored OPC-modified design units may be placed within the mask layout, and the flattened data may be colored. Thus, turnaround time for mask design is significantly improved since the numerically intensive OPC is performed on the hierarchical data, avoiding the need to perform OPC on flattened data, whereas the less intensive global coloring is performed on flattened data.

Abstract: An iterative timing analysis is analytically performed before a chip is fabricated, based on a methodology using optical proximity correction techniques for shortening the gate lengths and adjusting metal line widths and proximity distances of critical time sensitive devices. The additional mask is used as a selective trim to form shortened gate lengths or wider metal lines for the selected, predetermined transistors, affecting the threshold voltages and the RC time constants of the selected devices. Marker shapes identify a predetermined subgroup of circuitry that constitutes the devices in the critical timing path. The analysis methodology is repeated as often as needed to improve the timing of the circuit with shortened designed gate lengths and modified RC timing constants until manufacturing limits are reached. A mask is made for the selected critical devices using OPC techniques.

Abstract: A method for laying out process dummy cells in relationship to inside memory cells of a memory array includes (a) calculating an initial process performance parameter for the memory array; (b) changing dummy cell layout configuration for a layer electrically connected to inside cells; (c) applying lithographic simulation and yield model for both the inside memory cells and the changed layout configuration process dummy cells; and (d) repeating steps (b) and (c) until yield is maximized. Checks may be performed to ensure that there is enough room to make the change and that there is no significant adverse effect to neighboring circuits. The process performance parameter may be yield or a process window for the inside memory cells.

Abstract: A method of designing an integrated circuit is provided in which the design layout is optimized using a process model until the design constraints are satisfied by the image contours simulated by the process model. The process model used in the design phase need not be as accurate as the lithographic model used in preparing the lithographic mask layout during data prep. The resulting image contours are then included with the modified, optimized design layout to the data prep process, in which the mask layout is optimized using the lithographic process model, for example, including RET and OPC. The mask layout optimization matches the images simulated by the lithographic process model with the image contours generated during the design phase, which ensures that the design and manufacturability constraints specified by the designer are satisfied by the optimized mask layout.

Abstract: A method of designing a mask for projecting an image of an integrated circuit design in lithographic processing, wherein the integrated circuit layout has a plurality of segments of critical width. The method comprises creating a first mask design by aligning mask features used to assist in projecting critical width segments with the critical width segments of the integrated circuit design, such that the first mask design meets predetermined manufacturability design rules, and creating a second mask design by aligning mask features with the critical width segments of the integrated circuit design, such that the second mask design meets predetermined lithographic design rules in regions local to the critical width segments.

Abstract: A method of conveying the designer's intended electrical characteristics for a semiconductor design is provided by forming tolerance bands for a design layer of interest that take into consideration constraints from design layers that interact with and influence the features on the design layer of interest. The method determines regions, i.e. tolerance bands, within which the printed edges of features of the layer of interest will print within a predetermined criterion, and satisfy a variety of constraints, including, but not limited to, electrical, overlay and manufacturability constraints arising from the influence of features on other layers. The method may be implemented in a computer program product for execution on a computer system. The resulting tolerance bands can be used to efficiently convey the designer's intent to a lithographer, an OPC engineer or a mask manufacturer or tool.