Abstract: A method of forming a photolithographic mask layout with Sub-Resolution Assist Feature (SRAF) elements on a mask for correcting for proximity effects for a pattern imaged comprising the steps of developing a layout of mask features for printing main pattern features. Provide a table of SRAF element data including spacing of main pattern features and SRAF elements, applying SRAF elements to the mask layout as a function of spacing of main pattern features and SRAF elements, legalizing the SRAF elements as a function of style options, and providing a target pattern comprising a modified layout for the mask, identifying problem edge segments of an SRAF element of the target pattern at risk of causing a printing defect, applying a selected bias to the problem edge segments to modify the pattern where there are areas of SRAF element loss, and providing an output of a modified pattern with modified SRAF elements removing the areas of SRAF element loss.

Abstract: A method for model-based verification of resolution enhancement techniques (RET) and optical proximity correction (OPC) in lithography includes scaling shapes of a drawn mask layout to their corresponding intended wafer dimensions so as to create a scaled image. A first feature of the scaled image is shifted with respect to a second feature thereof in accordance with a predetermined maximum overlay error. An intersection parameter of the first and said second features of the scaled image is calculated so as to determine a yield metric of an ideal layout. A first feature of a simulated wafer image is shifted with respect to a second feature thereof in accordance with the predetermined maximum overlay error. An intersection parameter of the first and said second features of the simulated wafer image is calculated so as to determine a yield metric of a simulated layout, and the yield metric of the simulated wafer image is compared to the yield metric of the scaled image.

Abstract: A method of generating patterns of a pair of photomasks from a data set defining a circuit layout to be provided on a substrate includes identifying critical segments of the circuit layout to be provided on the substrate. Block mask patterns are generated and then legalized based on the identified critical segments. Thereafter, phase mask patterns are generated, legalized and colored. The legalized block mask patterns and the legalized phase mask patterns that have been colored define features of a block mask and an alternating phase shift mask, respectively, for use in a dual exposure method for patterning features in a resist layer of a substrate.

Abstract: A method of designing a mask for imaging an integrated circuit (IC) design layout is provided to efficiently configure subresolution assist features (SRAFs) corresponding to an optimally configured annular illumination source of a lithographic projection system. A critical pitch is identified for the IC design, and optimal inner and outer radial coordinates of an annular illumination source are determined so that the resulting image projected through the mask will be optimized for the full range of pitches in the design layout. A relationship is provided for determining an optimal inner radius and outer radius for the annular illumination source. The number and placement of SRAFs are added to the mask design so that the resulting range of pitches substantially correspond to the critical pitch. The method of configuring SRAFs so that the image will have optimal characteristics, such as good contrast and good depth of focus, is fast.

Abstract: A method is described for designing an alternating phase shifted mask (altPSM) by optimally selecting the width of phase shapes. The selection of optimal phase shape widths is achieved by providing a lithography metric that describes the relationship between phase shape width and the target image dimension such that the metric, such as process window or across chip linewidth variation (ACLV), is optimized. In a preferred embodiment, ACLV is computed by Monte Carlo simulation by providing a set of error distributions for lithographic parameters such as focus, dose, lens aberrations, and the like. Alternatively, a lookup table of optimal phase widths associated with target image dimensions may be provided. The resulting altPSM is characterized by phase shapes having widths that vary according to the widths of the target image dimensions.

Abstract: A method is provided for designing an altPSM mask including a substrate. The method includes the following steps. Provide a circuit layout. Identify critical elements of the circuit layout. Provide a cutoff layout dimension. Identify critical segments of the circuit layout which are critical elements with a sub-cutoff dimension less than the cutoff dimension. Create basic phase shapes associated with the critical segments. Remove layout violations from the phase shapes. Determine whether the widths of phase shapes associated with a critical segment have unequal narrower and wider widths. If YES, then widen each narrower phase shape to match the width of wider phase shape associated with the critical segment and repeat the steps starting with removal of layout violations until the test answer is NO. When the test answer is NO, provide a layout pattern to an output.

Abstract: A method and computer system is described for designing a conflict-free altPSM layout by first constructing a planar interlock graph without predefining phase shift shapes. Feature nodes of the graph represent critical elements, while connection nodes of the graph represent phase shape interactions. A pattern analysis of the interlock graph is performed to identify layout violations. Solutions for resolving layout conflicts are applied to the layout resulting in at least one conflict-free altPSM layout. Phase shapes are then applied to the conflict-free altPSM layout. Selection of an optimal solution can be made based on cost analysis.

Abstract: A method and apparatus for making phase shift masks are provided wherein an anti-reflective coating used on an opaque pattern layer of the mask fully covers the opaque pattern layer and has not been etched in the etching process to form the phase shift mask. A two-exposure method to form the phase shift mask is used wherein a photoresist having a defined dose-to-clear level is coated on the surface of the mask and the lower surface of the mask is exposed to a blanket exposure in an energy amount less than the dose-to-clear level. The open areas of the upper surface of the mask to be etched are exposed to an energy dose in an amount less than the dose-to-clear level, with the sum of the amounts of the lower surface energy and upper surface energy being at least the dose-to-clear level. The method and apparatus minimizes and/or avoids etching of the anti-reflective coating.

Abstract: A phase shift mask shape that reduces line-end shortening at the critical feature without changing layout size increases required of requisite phase shift rules. The phase feature is given an angled extension, which includes the lithographic shortening value. This allows the critical shape to be designed much closer to the reference layer then it could without the angled extension feature. Phase mask extension features beyond a given device segment are significantly reduced by lengthening the feature along an uncritical portion; moving the feature reference point to the device layer; and flattening the phase extension feature into an L-shape or T-shape along the uncritical parts of a device segment. Applying these design rules allows a draw of the gate conductor under current conditions and puts phase shapes inside without extending the gate conductor dimensions to the next feature.

Abstract: A method and computer program product is described for optimizing the design of a circuit layout that assigns binary properties to the design elements according to a hierarchy of rules. For example, the design of an alternating phase shifted mask (altPSM) is optimized first according to rules that assign phase shapes that maximize image quality for critical circuit elements, and then further optimized to minimize mask manufacturability problems without significantly increasing the complexity of the design process flow. Further optimization of the design according to additional rules can be performed in a sequentially decreasing priority order. As the priority of rules decrease, some violation of lower priority rules may be acceptable, as long as higher priority rules are not violated.

Abstract: A method is described for designing an alternating phase shifted mask (altPSM) by optimally selecting the width of phase shapes. The selection of optimal phase shape widths is achieved by providing a lithography metric that describes the relationship between phase shape width and the target image dimension such that the metric, such as process window or across chip linewidth variation (ACLV), is optimized. In a preferred embodiment, ACLV is computed by Monte Carlo simulation by providing a set of error distributions for lithographic parameters such as focus, dose, lens aberrations, and the like. Alternatively, a lookup table of optimal phase widths associated with target image dimensions may be provided. The resulting altPSM is characterized by phase shapes having widths that vary according to the widths of the target image dimensions.

Abstract: A method of forming a photolithographic mask layout with Sub-Resolution Assist Feature (SRAF) elements on a mask for correcting for proximity effects for a pattern imaged comprising the steps of developing a layout of mask features for printing main pattern features. Provide a table of SRAF element data including spacing of main pattern features and SRAF elements, applying SRAF elements to the mask layout as a function of spacing of main pattern features and SRAF elements, legalizing the SRAF elements as a function of style options, and providing a target pattern comprising a modified layout for the mask, identifying problem edge segments of an SRAF element of the target pattern at risk of causing a printing defect, applying a selected bias to the problem edge segments to modify the pattern where there are areas of SRAF element loss, and providing an output of a modified pattern with modified SRAF elements removing the areas of SRAF element loss.

Abstract: A method of designing a mask for imaging an integrated circuit (IC) design layout is provided to efficiently configure subresolution assist features (SRAFs) corresponding to an optimally configured annular illumination source of a lithographic projection system. A critical pitch is identified for the IC design, and optimal inner and outer radial coordinates of an annular illumination source are determined so that the resulting image projected through the mask will be optimized for the full range of pitches in the design layout. A relationship is provided for determining an optimal inner radius and outer radius for the annular illumination source. The number and placement of SRAFs are added to the mask design so that the resulting range of pitches substantially correspond to the critical pitch. The method of configuring SRAFs so that the image will have optimal characteristics, such as good contrast and good depth of focus, is fast.

Abstract: A method is described for designing an alternating phase shifted mask (altPSM) by optimally selecting the width of phase shapes. The selection of optimal phase shape widths is achieved by providing a lithography metric that describes the relationship between phase shape width and the target image dimension such that the metric, such as process window or across chip linewidth variation (ACLV), is optimized. In a preferred embodiment, ACLV is computed by Monte Carlo simulation by providing a set of error distributions for lithographic parameters such as focus, dose, lens aberrations, and the like. Alternatively, a lookup table of optimal phase widths associated with target image dimensions may be provided. The resulting altPSM is characterized by phase shapes having widths that vary according to the widths of the target image dimensions.

Abstract: A method is provided for designing an altPSM mask including a substrate. The method includes the following steps. Provide a circuit layout. Identify critical elements of the circuit layout. Provide a cutoff layout dimension. Identify critical segments of the circuit layout which are critical elements with a sub-cutoff dimension less than the cutoff dimension. Create basic phase shapes associated with the critical segments. Remove layout violations from the phase shapes. Determine whether the widths of phase shapes associated with a critical segment have unequal narrower and wider widths. If YES, then widen each narrower phase shape to match the width of wider phase shape associated with the critical segment and repeat the steps starting with removal of layout violations until the test answer is NO. When the test answer is NO, provide a layout pattern to an output.

Abstract: A method and computer system is described for designing a conflict-free altPSM layout by first constructing a planar interlock graph without predefining phase shift shapes. Feature nodes of the graph represent critical elements, while connection nodes of the graph represent phase shape interactions. A pattern analysis of the interlock graph is performed to identify layout violations. Solutions for resolving layout conflicts are applied to the layout resulting in at least one conflict-free altPSM layout. Phase shapes are then applied to the conflict-free altPSM layout. Selection of an optimal solution can be made based on cost analysis.

Abstract: A method and apparatus for making phase shift masks are provided wherein an anti-reflective coating used on an opaque pattern layer of the mask fully covers the opaque pattern layer and has not been etched in the etching process to form the phase shift mask. A two-exposure method to form the phase shift mask is used wherein a photoresist having a defined dose-to-clear level is coated on the surface of the mask and the lower surface of the mask is exposed to a blanket exposure in an energy amount less than the dose-to-clear level. The open areas of the upper surface of the mask to be etched are exposed to an energy dose in an amount less than the dose-to-clear level, with the sum of the amounts of the lower surface energy and upper surface energy being at least the dose-to-clear level. The method and apparatus minimizes and/or avoids etching of the anti-reflective coating.

Abstract: A method and computer program product is described for optimizing the design of a circuit layout that assigns binary properties to the design elements according to a hierarchy of rules. For example, the design of an alternating phase shifted mask (altPSM) is optimized first according to rules that assign phase shapes that maximize image quality for critical circuit elements, and then further optimized to minimize mask manufacturability problems without significantly increasing the complexity of the design process flow. Further optimization of the design according to additional rules can be performed in a sequentially decreasing priority order. As the priority of rules decrease, some violation of lower priority rules may be acceptable, as long as higher priority rules are not violated.

Abstract: A method and computer program product is described for optimizing the design of a circuit layout that assigns binary properties to the design elements according to a hierarchy of rules. For example, the design of an alternating phase shifted mask (altPSM) is optimized first according to rules that assign phase shapes that maximize image quality for critical circuit elements, and then further optimized to minimize mask manufacturability problems without significantly increasing the complexity of the design process flow. Further optimization of the design according to additional rules can be performed in a sequentially decreasing priority order. As the priority of rules decrease, some violation of lower priority rules may be acceptable, as long as higher priority rules are not violated.

Abstract: A method for generating an optical proximity correction (OPC) model includes generating a set of correction rules for a wafer design containing at least one of lines and assist features, determining a set of corrections that need to be made over a range of sizes and spaces of the lines and assist features based on the set of correction rules, and creating an optical proximity correction model for correcting the wafer design based on the set of corrections.