Patents by Inventor Laurent Grenouillet

Laurent Grenouillet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220223206
    Abstract: A matrix includes a plurality of volatile switches, each of the volatile switches including an active layer made of an OTS material, the plurality of volatile switches being divided into two groups in such a way as to form a message, each of the volatile switches of the first group having been initialized beforehand by an initialization voltage, none of the volatile switches of the second group having been initialized beforehand, the message being formed by the initialized or non-initialized states of each of the switches of the matrix.
    Type: Application
    Filed: January 13, 2022
    Publication date: July 14, 2022
    Inventors: Laurent GRENOUILLET, Anthonin VERDY
  • Publication number: 20220173163
    Abstract: A method for increasing the surface roughness of a layer based on a metal having a catalytic power, includes fixing fluorine or chlorine on the surface of the metal based layer, by exposing the metal based layer to a plasma formed from a reactive gas containing fluorine or chlorine; exposing the surface of the metal based layer to a humid environment to produce an acid, by reaction of hydrogen from the humid environment with the fluorine or the chlorine fixed on the surface of the metal based layer, the acid reacting with the metal to form residues, the whole of the residues forming a pattern on the surface of the metal based layer, and etching the metal based layer through the residues, so as to transfer the pattern into the metal based layer.
    Type: Application
    Filed: November 24, 2021
    Publication date: June 2, 2022
    Inventors: Nicolas POSSEME, Laurent GRENOUILLET, Olivier POLLET
  • Publication number: 20220172959
    Abstract: A method for increasing the surface roughness of a metal layer, includes depositing on the metal layer a sacrificial layer made of a dielectric material including nitrogen; exposing a surface of the sacrificial layer to an etching plasma so as to create asperities; and etching the metal layer through the sacrificial layer, so as to transfer the asperities of the sacrificial layer into a part at least of the metal layer.
    Type: Application
    Filed: November 26, 2021
    Publication date: June 2, 2022
    Inventors: Olivier POLLET, Laurent GRENOUILLET, Nicolas POSSEME
  • Publication number: 20220069217
    Abstract: Resistive memory cell provided with a first electrode and a second electrode arranged on either side of a dielectric layer and facing an interface between a first region and a second region, said first and second region having different compositions in terms of doping and/or dielectric constant, so as to confine the zone of reversible creation of a conductive filament at said interface.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 3, 2022
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Laurent GRENOUILLET, Marios BARLAS, Etienne NOWAK
  • Patent number: 11264479
    Abstract: A method of production of a field-effect transistor from a stack of layers forming a semiconductor-on-insulator type substrate, the stack including a superficial layer of an initial thickness, made of a crystalline semiconductor material and covered with a protective layer, the method including: defining, by photolithography, a gate pattern in the protective layer; etching the gate pattern into the superficial layer to leave a thickness of the layer of semiconductor material in place, the thickness defining a height of a conduction channel of the field-effect transistor; forming a gate in the gate pattern; forming, in the superficial layer and on either side of the gate, source and drain zones, while preserving, in the zones, the initial thickness of the superficial layer.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: March 1, 2022
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Laurent Grenouillet, Maud Vinet, Romain Wacquez
  • Patent number: 11189792
    Abstract: A resistive non-volatile memory cell includes a first electrode, a second electrode and an oxide layer disposed between the first electrode and the second electrode, the memory cell being capable of reversibly switching between: —a high resistance state obtained by applying a first bias voltage between the first electrode and the second electrode; and—a low resistance state obtained by applying a second bias voltage between the first electrode and the second electrode; the oxide layer including a switching zone forming a conduction path prioritised for the current passing through the memory cell when the memory cell is in the low resistance state. The oxide layer includes a first zone doped with aluminium or silicon, the aluminium or silicon being present in the first zone with an atomic concentration that is selected so as to locate the switching zone outside the first zone.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: November 30, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Laurent Grenouillet, Marios Barlas, Philippe Blaise, Benoît Sklenard, Elisa Vianello
  • Patent number: 11145663
    Abstract: A method of fabrication of a ferroelectric memory including a first electrode, a second electrode and a layer of active material made of hafnium dioxide HfO2 positioned between the first electrode and the second electrode, where the method includes depositing a first electrode layer; depositing the layer of active material; doping the layer of active material; depositing a second electrode layer; wherein the method includes sub-microsecond laser annealing of the layer of doped active material.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: October 12, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Laurent Grenouillet, Christelle Charpin-Nicolle, Jean Coignus, Terry Francois, Sébastien Kerdiles
  • Patent number: 10985317
    Abstract: A device for selecting a storage cell, includes a first electrode, a second electrode and an oxide layer disposed between the first electrode and the second electrode, wherein the oxide layer is doped with a first element from column IV of the periodic table.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: April 20, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Marios Barlas, Philippe Blaise, Laurent Grenouillet, Benoît Sklenard, Elisa Vianello
  • Patent number: 10777701
    Abstract: A photosensitive transistor device, on a semiconductor on insulator substrate, the photosensitive zone being formed in a substrate support layer and being arranged so that the concentration of photogenerated charges in the photosensitive zone can be increased towards a given zone facing the channel zone of the transistor.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: September 15, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Lina Kadura, Laurent Grenouillet, Olivier Rozeau, Alexei Tchelnokov
  • Publication number: 20200194442
    Abstract: A method of fabrication of a ferroelectric memory including a first electrode, a second electrode and a layer of active material made of hafnium dioxide HfO2 positioned between the first electrode and the second electrode, where the method includes depositing a first electrode layer; depositing the layer of active material; doping the layer of active material; depositing a second electrode layer; wherein the method includes sub-microsecond laser annealing of the layer of doped active material.
    Type: Application
    Filed: December 18, 2019
    Publication date: June 18, 2020
    Inventors: Laurent GRENOUILLET, Christelle CHARPIN-NICOLLE, Jean COIGNUS, Terry FRANCOIS, Sébastien KERDILES
  • Publication number: 20200127199
    Abstract: A device for selecting a storage cell, includes a first electrode, a second electrode and an oxide layer disposed between the first electrode and the second electrode, wherein the oxide layer is doped with a first element from column IV of the periodic table.
    Type: Application
    Filed: September 8, 2017
    Publication date: April 23, 2020
    Inventors: Mario BARLAS, Philippe BLAISE, Laurent GRENOUILLET, Benoît SKLENARD, Elisa VIANELLO
  • Patent number: 10453960
    Abstract: Field-effect transistor, the source and drain regions whereof are formed from a crystalline structure comprising: a first layer comprising two main faces parallel to one another and two lateral faces parallel to one another, the main faces being perpendicular to the lateral faces, a second layer overlapping the first layer, the second layer comprising a first main face and a second main face parallel to one another and two lateral faces, the first main face being in contact with the first layer, the lateral faces forming an angle ? in the range 50° to 59°, and preferably a 53° angle, with the first main face.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: October 22, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Vincent Mazzocchi, Laurent Grenouillet
  • Patent number: 10446564
    Abstract: The invention relates to a non-volatile memory that comprises selection transistors. Each selection transistor includes a layer of semiconductor material with a channel region and conduction electrodes, a gate stack including a gate electrode and a gate insulator, an isolation trench between the transistors, a storage structure of the RRAM type comprising a control electrode, and a dielectric layer formed under the control electrode and in the same material as the gate insulator, comprising a central part directly above the isolation trench and ends extending directly above conduction electrodes, and configured so as to form conducting filaments. The said storage structure and the said selection transistors are formed in the same pre-metallization layer.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: October 15, 2019
    Assignees: Commissariat a l'energie atomique et aux energies alternatives, Universite d'Aix-Marseille
    Inventors: Jean-Michel Portal, Marios Barlas, Laurent Grenouillet, Elisa Vianello
  • Publication number: 20190280203
    Abstract: A resistive non-volatile memory cell includes a first electrode, a second electrode and an oxide layer disposed between the first electrode and the second electrode, the memory cell being capable of reversibly switching between: —a high resistance state obtained by applying a first bias voltage between the first electrode and the second electrode; and—a low resistance state obtained by applying a second bias voltage between the first electrode and the second electrode; the oxide layer including a switching zone forming a conduction path prioritised for the current passing through the memory cell when the memory cell is in the low resistance state. The oxide layer includes a first zone doped with aluminium or silicon, the aluminium or silicon being present in the first zone with an atomic concentration that is selected so as to locate the switching zone outside the first zone.
    Type: Application
    Filed: September 8, 2017
    Publication date: September 12, 2019
    Inventors: Laurent GRENOUILLET, Marios BARLAS, Philippe BLAISE, Benoît SKLENARD, Elisa VIANELLO
  • Patent number: 10347721
    Abstract: There is provided a method for making a device including at least a strained semiconductor structure configured to form at least a transistor channel, including: forming, on a semiconductor layer, a sacrificial gate block and source and drain blocks on either side of the block, the semiconductor layer being a strained surface semiconductor layer disposed on an underlying insulating layer, with the underlying layer being disposed on an etch-stop layer; removing the block to form a cavity revealing a region of the strained surface layer configured to form the transistor channel; and etching, in the cavity, one or more portions of the region to define one or more semiconductor blocks and holes on either side, respectively, of the one or more blocks, the etching of holes extending into the underlying layer to form one or more galleries therein, etching of the galleries being stopped by the etch-stop layer.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: July 9, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Shay Reboh, Laurent Grenouillet, Raluca Tiron
  • Patent number: 10347545
    Abstract: There is provided a method for producing on a same substrate at least one first transistor and at least one second transistor that have different characteristics, the method including producing at least one first gate pattern and at least one second gate pattern on the substrate; depositing, on the first and the second gate patterns, at least: a first protective layer, and a second protective layer overlying the first protective layer and made of a material different from that of the first protective layer; masking of the second gate pattern by a masking layer; isotropic etching of the second protective layer; removing the masking layer; and anisotropic etching of the second protective layer selectively relative to the first protective layer.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: July 9, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIOUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Laurent Grenouillet, Sebastien Barnola, Marie-Anne Jaud, Jerome Mazurier, Nicolas Posseme
  • Publication number: 20190173005
    Abstract: A method for fabricating an OxRAM type memory location, including the steps of providing a stack including a superposition of a first layer that includes a first material made of Ti at more than 30% by mole fraction; a second layer made of HfO2 positioned under the first layer; via an ion implantation of a second material chosen from Xe, Kr or Ar in the first layer, carrying out an implantation of the first material in the second layer by collision with recoil effect in the first layer.
    Type: Application
    Filed: December 5, 2018
    Publication date: June 6, 2019
    Applicant: Commissariat a I'energie atomique et aux energies alternatives
    Inventors: Marios Barlas, Philippe Blaise, Laurent Grenouillet, Boubacar Traore
  • Patent number: 10290667
    Abstract: Photosensitive logic cell on a semiconductor-on-insulator substrate, possessing a P type transistor and an N type transistor fabricated on the front face of the substrate and whose respective threshold voltages can be modulated according to the quantity of photons received by a photosensitive zone provided opposite these transistors, the photosensitive zone possessing a photo-detection region whose arrangement is such that it favours illumination by the face of the photosensitive zone.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: May 14, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Olivier Rozeau, Laurent Grenouillet
  • Publication number: 20190074398
    Abstract: A photosensitive transistor device (T1), on a semiconductor on insulator substrate, the photosensitive zone (20) being formed in the substrate support layer and being arranged so that the concentration of photogenerated charges in the photosensitive zone can be increased towards a given zone facing the channel zone of the transistor.
    Type: Application
    Filed: August 28, 2018
    Publication date: March 7, 2019
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Lina Kadura, Laurent Grenouillet, Olivier Rozeau, Alexei Tchelnokov
  • Publication number: 20180331115
    Abstract: The invention relates to a non-volatile memory that comprises selection transistors. Each selection transistor includes a layer of semiconductor material with a channel region and conduction electrodes, a gate stack including a gate electrode and a gate insulator, an isolation trench between the transistors, a storage structure of the RRAM type comprising a control electrode, and a dielectric layer formed under the control electrode and in the same material as the gate insulator, comprising a central part directly above the isolation trench and ends extending directly above conduction electrodes, and configured so as to form conducting filaments. The said storage structure and the said selection transistors are formed in the same pre-metallization layer.
    Type: Application
    Filed: May 11, 2018
    Publication date: November 15, 2018
    Applicants: Commissariat a l'energie atomique et aux energies alternatives, Universite d'Aix-Marseille
    Inventors: Jean-Michel Portal, Marios Barlas, Laurent Grenouillet, Elisa Vianello