Abstract: The field effect transistor comprises a substrate successively comprising an electrically conducting support substrate, an electrically insulating layer and a semiconductor material layer. The counter-electrode is formed in a first portion of the support substrate facing the semi-conductor material layer. The insulating pattern surrounds the semi-conductor material layer to delineate a first active area and it penetrates partially into the support layer to delineate the first portion. An electrically conducting contact passes through the insulating pattern from a first lateral surface in contact with the counter-electrode through to a second surface. The contact is electrically connected to the counter-electrode.

Abstract: A microelectronic device is provided, including: a substrate including a first semiconductor layer positioned on a dielectric layer and a second semiconductor layer; and an isolation trench disposed through the first semiconductor layer, the dielectric layer, and a part of the thickness of the second semiconductor layer, including a dielectric material and delimiting, in the first semiconductor layer, a roughly rectangular active area of the device, wherein in said part of the thickness of the second semiconductor layer, at least one portion of the dielectric material is positioned under the active area delimited by at least four side walls of the trench, and two of the at least four side walls are roughly parallel with one another and are positioned under the active area, and the other two of the at least four side walls are orthogonal to said two walls and are not positioned under the active area.

Abstract: Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased.

Abstract: The present invention relates to a method for producing a microelectronic device having a channel structure formed from superimposed nanowires, in which a nanowire stack having a constant transverse section is firstly formed, followed by a sacrificial gate and insulating spacers, where source and drain areas are then formed by growth of semiconductor material on areas of the stack which are not protected by the sacrificial gate and the insulating spacers (FIG. 4D).

Abstract: A Method for making a separation between an active zone of a substrate located on its front face from a given portion of the substrate located on its back face, wherein trenches and cavities wider than the trenches are formed to extend said trenches, such that at least one given cavity formed to extend a given trench is adjacent to another cavity, and when the cavities have been filled with a given material, they form a separation zone between said active zone and a given portion of the substrate that will be removed later.

Abstract: Trenches are formed through a top semiconductor layer and a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A selective epitaxy is performed to form bulk semiconductor portions filling the trenches and in epitaxial alignment with the semiconductor material of a handle substrate. At least one dielectric layer is deposited over the top semiconductor layer and the bulk semiconductor portions, and is patterned to form openings over selected areas of the top semiconductor layer and the bulk semiconductor portions. A semiconductor alloy material is deposited within the openings directly on physically exposed surfaces of the top semiconductor layer and the bulk semiconductor portions. The semiconductor alloy material intermixes with the underlying semiconductor materials in a subsequent anneal.

Abstract: The substrate is provided with a first semiconducting area partially covered by a first masking pattern to define a protected surface and an open surface. A continuous layer of silicon-germanium is deposited in non-selective manner on the first semiconducting area and on the first gate pattern. The continuous silicon-germanium layer forms an interface with the first semiconducting area. A diffusion/condensation annealing is performed to make the germanium atoms diffuse from the silicon-germanium layer to the open surface of the first semiconducting area. The masking pattern is a gate stack of the transistor or is used to define the shape of the gate stack in an electrically insulating layer so as to form a self-aligned gate stack with the source and drain areas.

Abstract: An image sensor device is provided, including at least one transistor lying on a semiconductor-on-insulator substrate that includes a semi-conducting layer, in which a channel area of the transistor is disposed in a portion thereof, and an insulating layer separating the semi-conducting layer from a semi-conducting support layer, wherein the semi-conducting layer and the insulating layer extend beyond the channel area, and extend under at least a portion of source/drain regions of the transistor, wherein the semi-conducting support layer includes at least one photosensitive area including at least one P-doped region and at least one N-doped region forming a junction, the photosensitive area being disposed facing the transistor on a side of the channel area thereof and opposite a side of a gate electrode thereof, and wherein the insulating layer is configured to provide a capacitive coupling between the photosensitive area and the semi-conducting layer.

Abstract: The semiconductor-on-insulator substrate includes a support, an electrically insulating film, a crystalline film made from semiconductor material, and a protection layer. Germanium ions are implanted in the semiconductor material film through the protection layer so as to form an amorphized area in contact with the protection layer and a crystalline area in contact with the electrically insulating film. The semiconductor material film is annealed so as to recrystallize the amorphized area from the crystalline area.

Abstract: Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased.

Abstract: A method of forming a semiconductor-on-insulator (SOI) device includes defining a shallow trench isolation (STI) structure in an SOI substrate, the SOI substrate including a bulk layer, a buried insulator (BOX) layer over the bulk layer, and an SOI layer over the BOX layer; forming a doped region in a portion of the bulk layer corresponding to a lower location of the STI structure, the doped region extending laterally into the bulk layer beneath the BOX layer; selectively etching the doped region of the bulk layer with respect to undoped regions of the bulk layer such that the lower location of the STI structure undercuts the BOX layer; and filling the STI structure with an insulator fill material.

Abstract: A method for manufacturing a fin MOS transistor from an SOI-type structure including a semiconductor layer on a silicon oxide layer coating a semiconductor support, this method including the steps of: a) forming, from the surface of the semiconductor layer, at least one trench delimiting at least one fin in the semiconductor layer and extending all the way to the surface of the semiconductor support; b) etching the sides of a portion of the silicon oxide layer located under the fin to form at least one recess under the fin; and c) filling the recess with a material selectively etchable over silicon oxide.

Abstract: A method for producing one or plural trenches in a device comprising a substrate of the semiconductor on insulator type formed by a semiconductive support layer, an insulating layer resting on the support layer and a semiconductive layer resting on said insulating layer, the method comprising steps of: a) localised doping of a given portion of said insulating layer through an opening in a masking layer resting on the fine semiconductive layer, b) selective removal of said given doped area at the bottom of said opening.

Abstract: A light-emitting microelectronic device including a first N-type transistor (T1) and a second P-type transistor (T2), the respective gates of which are formed opposite one another, either side of an intrinsic semiconductor material region.

Abstract: The field effect device is formed on a substrate of semiconductor on insulator type provided with a support substrate separated from a semiconductor film by an electrically insulating layer. The source and drain electrodes are formed in the semiconductor film on each side of the gate electrode. The electrically insulating layer comprises a first area having a first electric capacitance value between the semiconductor film and the support substrate facing the gate electrode. The electrically insulating layer comprises second and third areas having a higher electric capacitance value than the first value between the semiconductor film and the support substrate facing the source and drain electrodes.

Abstract: The semiconductor-on-insulator substrate includes a support, an electrically insulating film, a crystalline film made from semiconductor material, and a protection layer. Germanium ions are implanted in the semiconductor material film through the protection layer so as to form an amorphized area in contact with the protection layer and a crystalline area in contact with the electrically insulating film. The semiconductor material film is annealed so as to recrystallize the amorphized area from the crystalline area.

Abstract: The substrate successively includes a support substrate, an electrically insulating layer, a semiconductor material layer, and a gate pattern. The semiconductor material layer and gate pattern are covered by a covering layer. A first doping impurity is implanted in the semiconductor material layer through the covering layer so as to place the thickness of maximum concentration of the first doping impurity in the first layer. The covering layer is partly eliminated so as to form lateral spacers leaving source/drain electrodes free.

Abstract: Method of producing a photonic device including at least one light source and at least one photodetector on a structure including a waveguide layer, this method comprising the following steps: a) growing successively on a substrate (10), a photodetection structure (11) and a light source structure (12), the photodetection structure and the light source structure being made of a stack of layers, the light source layers being stacked on top of the photodetector layers and both structures sharing one of these layers.

Abstract: A microelectronic device including: a substrate including a first semiconductor layer positioned on a dielectric layer and a second semiconductor layer, an isolation trench made through the first semiconductor layer, the dielectric layer and a part of the thickness of the second semiconductor layer, including at least one dielectric material and delimiting, in the first semiconductor layer, at least one rectangular active area of the device, and in which, in said part of the thickness of the second semiconductor layer, at least one portion of dielectric material of the isolation trench is positioned under the active area by forming two side walls, two other side walls of the isolation trench being not arranged under the active area.

Abstract: The field effect device comprises a sacrificial gate electrode having side walls covered by lateral spacers formed on a semiconductor material film. The source/drain electrodes are formed in the semiconductor material film and are arranged on each side of the gate electrode. A diffusion barrier element is implanted through the void left by the sacrificial gate so as to form a modified diffusion area underneath the lateral spacers. The modified diffusion area is an area where the mobility of the doping impurities is reduced compared with the source/drain electrodes.