Abstract: The invention relates to a process for fabricating an integrated circuit (1), comprising the steps of: providing a substrate (100), the substrate being equipped with first and second dummy gates and with an encapsulation layer (106); removing the first and second dummy gates in order to make first and second grooves (23, 33) in said encapsulation layer (106); simultaneously depositing a gate insulating layer (107) at least in the bottom of the first groove and on a side wall of the second groove; forming a gate electrode of said transistor (2) in the first groove, forming source and drain electrodes of said transistor on either side of said gate electrode, forming first and second electrodes of said memory cell on either side of said gate insulating layer deposited on a side wall of the second groove.

Abstract: The invention relates to an integrated circuit (1), comprising: a field-effect transistor (2), comprising: first and second conduction electrodes (201, 202); a channel zone (203) arranged between the first and second conduction electrodes; a gate stack (220) arranged vertically in line with the channel zone, and comprising a gate electrode (222); an RRAM-type memory point (31) formed under the channel zone, or formed in the gate stack under the gate electrode.

Abstract: A fin MOS transistor is made from an SOI-type structure that includes a semiconductor layer on a silicon oxide layer coating a semiconductor support. A trench formed from the surface of the semiconductor layer delimits at least one fin in the semiconductor layer, that trench extending at least to an upper surface of the semiconductor support. Etched recesses in sides of a portion of the silicon oxide layer located under the fin are filled with a material selectively etchable over silicon oxide.

Abstract: Photosensitive logic cell on a semiconductor-on-insulator substrate, possessing a P type transistor and an N type transistor fabricated on the front face of the substrate and whose respective threshold voltages can be modulated according to the quantity of photons received by a photosensitive zone provided opposite these transistors, the photosensitive zone possessing a photo-detection region whose arrangement is such that it favours illumination by the face of the photosensitive zone.

Abstract: A method for manufacturing a microelectronic device with transistors of different types having raised source and drain regions and different overlap regions.

Abstract: A method of making crystal semi-conducting material-based elements, including providing a support having amorphous semi-conducting material-based semi-conducting elements, the support being further provided with one or more components and with a reflective protective area configured so as to reflect a light radiation in a given wavelength range, exposing the element(s) to a laser radiation emitting in the given wavelength range so as to recrystallize the elements, the reflective protective area being arranged on the support relative to the elements and to the components so as to reflect the laser radiation and protect the components from this radiation.

Abstract: An integrated circuit, including: a UTBOX layer; a first cell, including: FDSOI transistors; a first STI separating the transistors; a first ground plane located beneath one of the transistors and beneath the UTBOX layer; a first well; a second cell, including: FDSOI transistors; a second STI separating the transistors; a second ground plane located beneath one of the transistors and beneath the UTBOX layer; a second well; a third STI separating the cells, reaching the bottom of the first and second wells; a deep well extending continuously beneath the first and second wells, having a portion beneath the third STI whose doping density is at least 50% higher than the doping density of the deep well beneath the first and second STIs.

Abstract: Method for creation of stressed channel structure transistors wherein at least one amorphising ion implantation of the surface layer of a substrate of the semiconductor-on-insulator type is carried out through openings in a mask, so as to render zones of the surface layers amorphous and to induce relaxation of a zone intended to form a channel and located between the zones that have been rendered amorphous, the relaxation being carried out in a direction orthogonal to that in which it is intended that the channel current flows.

Abstract: The invention provides a method of etching a crystalline semiconductor material (114), the method being characterized in that it comprises: at least one ion implantation performed by implanting a plurality of ions (121) in at least one volume (113) of the semiconductor material (114) in such a manner as to make the semiconductor material amorphous in the at least one implanted volume (113), and as to keep the semiconductor material (114) in a crystalline state outside (112) the at least one implanted volume (113); and at least one chemical etching for selectively etching the amorphous semiconductor material relative to the crystalline semiconductor material, so as to remove the semiconductor material in the at least one volume (113) and so as to keep the semiconductor material outside (112) the at least one volume (113).

Abstract: An integrated circuit, including: a first cell, including: FDSOI transistors; a UTBOX layer lying beneath the transistors; a first well lying beneath the insulator layer and beneath the transistors, the first well having a first type of doping; a first ground plane having a second type of doping, located beneath one of the transistors and between the insulator layer and the first well; a first STI separating the transistors and crossing the insulator layer; a first conductive element forming an electrical connection between the first well and the first ground plane, located under the first STI; a second cell including a second well; a second STI separating the cells, crossing the insulator layer and reaching the bottom of the first and second wells.

Abstract: Method to strain a channel zone of a transistor of the semiconductor on insulator type transistor that makes use of an SMT stress memorization technique in which regions located under the insulation layer of the substrate (FIG. 6) are amorphized, before the transistor gate is made.

Abstract: The invention relates to a process for fabricating an integrated circuit (1), comprising the steps of: providing a substrate (100), the substrate being equipped with first and second dummy gates and with an encapsulation layer (106); removing the first and second dummy gates in order to make first and second grooves (23, 33) in said encapsulation layer (106); simultaneously depositing a gate insulating layer (107) at least in the bottom of the first groove and on a side wall of the second groove; forming a gate electrode of said transistor (2) in the first groove, forming source and drain electrodes of said transistor on either side of said gate electrode, forming first and second electrodes of said memory cell on either side of said gate insulating layer deposited on a side wall of the second groove.

Abstract: Methods and structures for forming uniaxially-strained, nanoscale, semiconductor bars from a biaxially-strained semiconductor layer are described. A spatially-doubled mandrel process may be used to form a mask for patterning dense, narrow trenches through the biaxially-strained semiconductor layer. The resulting slicing of the biaxially-strained layer enhances carrier mobility and can increase device performance.

Abstract: A method of producing a microelectronic device in a substrate comprising a first semiconductor layer, a dielectric layer and a second semiconductor layer, comprising the following steps: etching a trench through the first semiconductor layer, the dielectric layer and a part of the thickness of the second semiconductor layer, thus defining, in the first semiconductor layer, one active region of the microelectronic device, ionic implantation in one or more side walls of the trench, at the level of the second semiconductor layer, modifying the crystallographic properties and/or the chemical properties of the implanted semiconductor, etching of the implanted semiconductor such that at least a part of the trench extends under a part of the active region, —filling of the trench with a dielectric material, forming an isolation trench surrounding the active region and comprising portions extending under a part of the active region.

Abstract: The substrate is provided with a first semiconducting area partially covered by a first masking pattern to define a protected surface and an open surface. A continuous layer of silicon-germanium is deposited in non-selective manner on the first semiconducting area and on the first gate pattern. The continuous silicon-germanium layer forms an interface with the first semiconducting area. A diffusion/condensation annealing is performed to make the germanium atoms diffuse from the silicon-germanium layer to the open surface of the first semiconducting area. The masking pattern is a gate stack of the transistor or is used to define the shape of the gate stack in an electrically insulating layer so as to form a self-aligned gate stack with the source and drain areas.

Abstract: Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased.

Abstract: Methods and structures for forming uniaxially-strained, nanoscale, semiconductor bars from a biaxially-strained semiconductor layer are described. A spatially-doubled mandrel process may be used to form a mask for patterning dense, narrow trenches through the biaxially-strained semiconductor layer. The resulting slicing of the biaxially-strained layer enhances carrier mobility and can increase device performance.

Abstract: A transistor includes an active layer forming a channel for the transistor, an insulating layer disposed facing a lower face of the active layer, a gate turned toward an upper face of the active layer and a source and a drain disposed on both sides of the gate. At least one among the source and the drain extends at least partly through the active layer and into the insulating layer.

Abstract: A method of making crystal semi-conducting material-based elements, including providing a support having amorphous semi-conducting material-based semi-conducting elements, the support being further provided with one or more components and with a reflective protective area configured so as to reflect a light radiation in a given wavelength range, exposing the element(s) to a laser radiation emitting in the given wavelength range so as to recrystallize the elements, the reflective protective area being arranged on the support relative to the elements and to the components so as to reflect the laser radiation and protect the components from this radiation.

Abstract: A fin MOS transistor is made from an SOI-type structure that includes a semiconductor layer on a silicon oxide layer coating a semiconductor support. A trench formed from the surface of the semiconductor layer delimits at least one fin in the semiconductor layer, that trench extending at least to an upper surface of the semiconductor support. Etched recesses in sides of a portion of the silicon oxide layer located under the fin are filled with a material selectively etchable over silicon oxide.