Patents by Inventor Laurent Grenouillet
Laurent Grenouillet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10446564Abstract: The invention relates to a non-volatile memory that comprises selection transistors. Each selection transistor includes a layer of semiconductor material with a channel region and conduction electrodes, a gate stack including a gate electrode and a gate insulator, an isolation trench between the transistors, a storage structure of the RRAM type comprising a control electrode, and a dielectric layer formed under the control electrode and in the same material as the gate insulator, comprising a central part directly above the isolation trench and ends extending directly above conduction electrodes, and configured so as to form conducting filaments. The said storage structure and the said selection transistors are formed in the same pre-metallization layer.Type: GrantFiled: May 11, 2018Date of Patent: October 15, 2019Assignees: Commissariat a l'energie atomique et aux energies alternatives, Universite d'Aix-MarseilleInventors: Jean-Michel Portal, Marios Barlas, Laurent Grenouillet, Elisa Vianello
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Publication number: 20190280203Abstract: A resistive non-volatile memory cell includes a first electrode, a second electrode and an oxide layer disposed between the first electrode and the second electrode, the memory cell being capable of reversibly switching between: —a high resistance state obtained by applying a first bias voltage between the first electrode and the second electrode; and—a low resistance state obtained by applying a second bias voltage between the first electrode and the second electrode; the oxide layer including a switching zone forming a conduction path prioritised for the current passing through the memory cell when the memory cell is in the low resistance state. The oxide layer includes a first zone doped with aluminium or silicon, the aluminium or silicon being present in the first zone with an atomic concentration that is selected so as to locate the switching zone outside the first zone.Type: ApplicationFiled: September 8, 2017Publication date: September 12, 2019Inventors: Laurent GRENOUILLET, Marios BARLAS, Philippe BLAISE, Benoît SKLENARD, Elisa VIANELLO
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Patent number: 10347721Abstract: There is provided a method for making a device including at least a strained semiconductor structure configured to form at least a transistor channel, including: forming, on a semiconductor layer, a sacrificial gate block and source and drain blocks on either side of the block, the semiconductor layer being a strained surface semiconductor layer disposed on an underlying insulating layer, with the underlying layer being disposed on an etch-stop layer; removing the block to form a cavity revealing a region of the strained surface layer configured to form the transistor channel; and etching, in the cavity, one or more portions of the region to define one or more semiconductor blocks and holes on either side, respectively, of the one or more blocks, the etching of holes extending into the underlying layer to form one or more galleries therein, etching of the galleries being stopped by the etch-stop layer.Type: GrantFiled: September 21, 2017Date of Patent: July 9, 2019Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Shay Reboh, Laurent Grenouillet, Raluca Tiron
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Patent number: 10347545Abstract: There is provided a method for producing on a same substrate at least one first transistor and at least one second transistor that have different characteristics, the method including producing at least one first gate pattern and at least one second gate pattern on the substrate; depositing, on the first and the second gate patterns, at least: a first protective layer, and a second protective layer overlying the first protective layer and made of a material different from that of the first protective layer; masking of the second gate pattern by a masking layer; isotropic etching of the second protective layer; removing the masking layer; and anisotropic etching of the second protective layer selectively relative to the first protective layer.Type: GrantFiled: May 19, 2017Date of Patent: July 9, 2019Assignee: COMMISSARIAT A L'ENERGIE ATOMIOUE ET AUX ENERGIES ALTERNATIVESInventors: Laurent Grenouillet, Sebastien Barnola, Marie-Anne Jaud, Jerome Mazurier, Nicolas Posseme
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Publication number: 20190173005Abstract: A method for fabricating an OxRAM type memory location, including the steps of providing a stack including a superposition of a first layer that includes a first material made of Ti at more than 30% by mole fraction; a second layer made of HfO2 positioned under the first layer; via an ion implantation of a second material chosen from Xe, Kr or Ar in the first layer, carrying out an implantation of the first material in the second layer by collision with recoil effect in the first layer.Type: ApplicationFiled: December 5, 2018Publication date: June 6, 2019Applicant: Commissariat a I'energie atomique et aux energies alternativesInventors: Marios Barlas, Philippe Blaise, Laurent Grenouillet, Boubacar Traore
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Patent number: 10290667Abstract: Photosensitive logic cell on a semiconductor-on-insulator substrate, possessing a P type transistor and an N type transistor fabricated on the front face of the substrate and whose respective threshold voltages can be modulated according to the quantity of photons received by a photosensitive zone provided opposite these transistors, the photosensitive zone possessing a photo-detection region whose arrangement is such that it favours illumination by the face of the photosensitive zone.Type: GrantFiled: October 26, 2016Date of Patent: May 14, 2019Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Olivier Rozeau, Laurent Grenouillet
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Publication number: 20190074398Abstract: A photosensitive transistor device (T1), on a semiconductor on insulator substrate, the photosensitive zone (20) being formed in the substrate support layer and being arranged so that the concentration of photogenerated charges in the photosensitive zone can be increased towards a given zone facing the channel zone of the transistor.Type: ApplicationFiled: August 28, 2018Publication date: March 7, 2019Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Lina Kadura, Laurent Grenouillet, Olivier Rozeau, Alexei Tchelnokov
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Publication number: 20180331115Abstract: The invention relates to a non-volatile memory that comprises selection transistors. Each selection transistor includes a layer of semiconductor material with a channel region and conduction electrodes, a gate stack including a gate electrode and a gate insulator, an isolation trench between the transistors, a storage structure of the RRAM type comprising a control electrode, and a dielectric layer formed under the control electrode and in the same material as the gate insulator, comprising a central part directly above the isolation trench and ends extending directly above conduction electrodes, and configured so as to form conducting filaments. The said storage structure and the said selection transistors are formed in the same pre-metallization layer.Type: ApplicationFiled: May 11, 2018Publication date: November 15, 2018Applicants: Commissariat a l'energie atomique et aux energies alternatives, Universite d'Aix-MarseilleInventors: Jean-Michel Portal, Marios Barlas, Laurent Grenouillet, Elisa Vianello
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Publication number: 20180261697Abstract: Field-effect transistor, the source and drain regions whereof are formed from a crystalline structure comprising: a first layer comprising two main faces parallel to one another and two lateral faces parallel to one another, the main faces being perpendicular to the lateral faces, a second layer overlapping the first layer, the second layer comprising a first main face and a second main face parallel to one another and two lateral faces, the first main face being in contact with the first layer, the lateral faces forming an angle ? in the range 50° to 59°, and preferably a 53° angle, with the first main face.Type: ApplicationFiled: March 12, 2018Publication date: September 13, 2018Applicant: Commissariat A L'Energie Atomique Et Aux Energies AlternativesInventors: Vincent Mazzocchi, Laurent Grenouillet
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Patent number: 10026657Abstract: A method is provided for producing at least one first transistor and at least one second transistor on the same substrate, including producing at least one first gate pattern and at least one second gate pattern on the substrate; depositing at least one first protective layer on the first and the second gate patterns; depositing, on the first and the second gate patterns, at least a first protective layer and a second protective layer overlying the first protective layer, the second protective layer being made from a different material than that of the first protective layer; masking the second gate pattern by a masking layer; isotropic etching of the second protective layer; removing the masking layer; and anisotropic etching of the second protective layer selectively relative to the first protective layer.Type: GrantFiled: May 19, 2017Date of Patent: July 17, 2018Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Nicolas Posseme, Laurent Grenouillet
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Patent number: 10014183Abstract: A method for producing at least one pattern in a layer resting on a substrate, including: a) making amorphous at least one first block of an upper layer of crystalline material resting on a first amorphous supporting layer, while the crystalline structure of a second block of the upper layer that adjoins and is juxtaposed with the first block is preserved; b) partially recrystallizing the first block by using at least one side surface of the second block that is in contact with the first block as an area for the start of a recrystallization front, the partial recrystallization being carried out to preserve a region of amorphous material in the first block; c) selectively etching the amorphous material of the upper layer with respect to the crystalline material of the upper layer to form at least one first pattern in the upper layer.Type: GrantFiled: November 9, 2015Date of Patent: July 3, 2018Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS SAInventors: Shay Reboh, Laurent Grenouillet, Yves Morand
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Patent number: 9935019Abstract: Method for creation of stressed channel structure transistors wherein at least one amorphizing ion implantation of the surface layer of a substrate of the semiconductor-on-insulator type is carried out through openings in a mask, so as to render zones of the surface layers amorphous and to induce relaxation of a zone intended to form a channel and located between the zones that have been rendered amorphous, the relaxation being carried out in a direction orthogonal to that in which it is intended that the channel current flows.Type: GrantFiled: September 9, 2016Date of Patent: April 3, 2018Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Shay Reboh, Laurent Grenouillet, Frederic Milesi, Yves Morand, Francois Rieutord
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Publication number: 20180082837Abstract: Realisation of a device comprising a transistor channel strained semiconductor structure, comprising: a) the formation, on a strained semiconductor layer, of a sacrificial gate block and of source and drain blocks on either side of the sacrificial gate block, b) removal of the sacrificial gate block so as to form a cavity, c) etching, in the cavity, of one or more portions of the region so as to define at least a semiconductor block and slots on either side of the semiconductor block.Type: ApplicationFiled: September 21, 2017Publication date: March 22, 2018Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Shay REBOH, Laurent GRENOUILLET, Raluca TIRON
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Patent number: 9911820Abstract: A method of fabrication, including the steps for supplying a substrate including a layer of semiconductor material covered by a sacrificial gate including a sacrificial gate insulator including a middle part, and edges covered by sacrificial spacers and having a thickness tox; removal of the sacrificial gate insulator and the sacrificial gate material; formation of a conformal deposition of thickness thk of dielectric material inside of the groove formed in order to form a gate insulator, with tox>thk?tox/2; formation of a gate electrode within the groove; removal of the sacrificial spacers so as to open up edges of the gate insulator layer; formation of spacers on the edges of the gate insulator layer on either side of the gate electrode, these spacers having a dielectric constant at the most equal to 3.5.Type: GrantFiled: March 21, 2017Date of Patent: March 6, 2018Assignees: Commissariat A L'Energie Atomique et aux Energies Alternatives, STMicroelectronics SA, STMicroelectronics (Crolles 2) SASInventors: Cyrille Le Royer, Frederic Boeuf, Laurent Grenouillet, Louis Hutin, Yves Morand
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Publication number: 20170358459Abstract: A method for producing at least one pattern in a layer resting on a substrate, including: a) making amorphous at least one first block of an upper layer of crystalline material resting on a first amorphous supporting layer, while the crystalline structure of a second block of the upper layer that adjoins and is juxtaposed with the first block is preserved; b) partially recrystallizing the first block by using at least one side surface of the second block that is in contact with the first block as an area for the start of a recrystallization front, the partial recrystallization being carried out to preserve a region of amorphous material in the first block; c) selectively etching the amorphous material of the upper layer with respect to the crystalline material of the upper layer to form at least one first pattern in the upper layer.Type: ApplicationFiled: November 9, 2015Publication date: December 14, 2017Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS SAInventors: Shay REBOH, Laurent GRENOUILLET, Yves MORAND
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Publication number: 20170358502Abstract: There is provided a method for producing on a same substrate at least one first transistor and at least one second transistor that have different characteristics, the method including producing at least one first gate pattern and at least one second gate pattern on the substrate; depositing, on the first and the second gate patterns, at least: a first protective layer, and a second protective layer overlying the first protective layer and made of a material different from that of the first protective layer; masking of the second gate pattern by a masking layer; isotropic etching of the second protective layer; removing the masking layer; and anisotropic etching of the second protective layer selectively relative to the first protective layer.Type: ApplicationFiled: May 19, 2017Publication date: December 14, 2017Applicant: Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Laurent GRENOUILLET, Sebastien BARNOLA, Marie-Anne JAUD, Jerome MAZURIER, Nicolas POSSEME
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Patent number: 9841657Abstract: Photosensitive logic inverter, in particular of the CMOS type, formed of a transistor of type P and of a transistor of type N of which the respective threshold voltages can be modulated according to the quantity of photons received by a photosensitive zone provided opposite these transistors.Type: GrantFiled: May 22, 2015Date of Patent: December 12, 2017Assignee: Commissariat à l'énergie atomique et aux énergies alternativesInventors: Laurent Grenouillet, Olivier Rozeau
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Patent number: 9831288Abstract: The invention relates to an integrated circuit (1), comprising: a field-effect transistor (2), comprising: first and second conduction electrodes (201, 202); a channel zone (203) arranged between the first and second conduction electrodes; a gate stack (220) arranged vertically in line with the channel zone, and comprising a gate electrode (222); an RRAM-type memory point (31) formed under the channel zone, or formed in the gate stack under the gate electrode.Type: GrantFiled: December 22, 2016Date of Patent: November 28, 2017Assignees: Commissariat A L'Energie Atomique et aux Energies Alternatives, STMicroelectronics (Crolles 2) SAS, STMicroelectronics SAInventors: Laurent Grenouillet, Sotirios Athanasiou, Philippe Galy
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Publication number: 20170338157Abstract: A method is provided for producing at least one first transistor and at least one second transistor on the same substrate, including producing at least one first gate pattern and at least one second gate pattern on the substrate; depositing at least one first protective layer on the first and the second gate patterns; depositing, on the first and the second gate patterns, at least a first protective layer and a second protective layer overlying, the first protective layer, the second protective layer being made from a different material than that of the first protective layer; masking the second gate pattern by a masking layer; isotropic etching of the second protective layer; removing the masking layer; and anisotropic etching of the second protective layer selectively relative to the first protective layer.Type: ApplicationFiled: May 19, 2017Publication date: November 23, 2017Applicant: Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Nicolas POSSEME, Laurent GRENOUILLET
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Publication number: 20170271470Abstract: A method of fabrication, including the steps for supplying a substrate including a layer of semiconductor material covered by a sacrificial gate including a sacrificial gate insulator including a middle part, and edges covered by sacrificial spacers and having a thickness tox; removal of the sacrificial gate insulator and the sacrificial gate material; formation of a conformal deposition of thickness thk of dielectric material inside of the groove formed in order to form a gate insulator, with tox>thk?tox/2; formation of a gate electrode within the groove; removal of the sacrificial spacers so as to open up edges of the gate insulator layer; formation of spacers on the edges of the gate insulator layer on either side of the gate electrode, these spacers having a dielectric constant at the most equal to 3.5.Type: ApplicationFiled: March 21, 2017Publication date: September 21, 2017Applicants: Commissariat a I'energie atomique et aux energies alternatives, STMicroelectronics SA, STMicroelectronics (Crolles 2) SASInventors: Cyrille LE ROYER, Frederic Boeuf, Laurent Grenouillet, Louis Hutin, Yves Morand