Patents by Inventor Laurent Grenouillet

Laurent Grenouillet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130302955
    Abstract: The present invention relates to a method for producing a microelectronic device having a channel structure formed from superimposed nanowires, in which a nanowire stack having a constant transverse section is firstly formed, followed by a sacrificial gate and insulating spacers, where source and drain areas are then formed by growth of semiconductor material on areas of the stack which are not protected by the sacrificial gate and the insulating spacers (FIG. 4D).
    Type: Application
    Filed: April 15, 2013
    Publication date: November 14, 2013
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT
    Inventors: MAUD VINET, SYLVAIN BARRAUD, LAURENT GRENOUILLET
  • Publication number: 20130189825
    Abstract: A method for producing one or plural trenches in a device comprising a substrate of the semiconductor on insulator type formed by a semiconductive support layer, an insulating layer resting on the support layer and a semiconductive layer resting on said insulating layer, the method comprising steps of: a) localised doping of a given portion of said insulating layer through an opening in a masking layer resting on the fine semiconductive layer, b) selective removal of said given doped area at the bottom of said opening.
    Type: Application
    Filed: July 23, 2012
    Publication date: July 25, 2013
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT.
    Inventors: Yannick LE TIEC, Laurent GRENOUILLET, Maud VINET
  • Patent number: 8487340
    Abstract: The invention relates to a method for making optoelectronic devices comprising nanowire semiconductors, in which: the nanowires (2) are formed on a substrate (1), said nanowires being capable of emitting a light beam; a first electric contact area is formed at the substrate, and a second electric contact area is formed at the nanowires, characterized in that the second electric contact area is formed on the edge of the nanowires (2) in direct contact with said nanowires, on a predetermined height (h) thereof and in the vicinity of their end opposite the substrate, as well as between said nanowires, the upper surface (20) of the nanowires being exposed.
    Type: Grant
    Filed: October 22, 2008
    Date of Patent: July 16, 2013
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Philippe Gilet, Laurent Grenouillet
  • Patent number: 8472493
    Abstract: A method for introducing light into a waveguide formed on the upper surface of a microelectronics substrate, by means of a distributed feedback laser device formed by the association of an SOI-type structure having a portion forming said waveguide, of a stack of III-V semiconductor gain materials partially covering the waveguide, and of an optical grating, wherein the grating step is selected so that the optical power of the laser beam circulates in a loop from the III-V stack to the waveguide.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: June 25, 2013
    Assignee: Commissariat a l'Energie Atomique et Aux Energies Alternatives
    Inventors: Tiphaine Dupont, Laurent Grenouillet
  • Publication number: 20120256262
    Abstract: The field effect transistor comprises a substrate successively comprising an electrically conducting support substrate, an electrically insulating layer and a semiconductor material layer. The counter-electrode is formed in a first portion of the support substrate facing the semi-conductor material layer. The insulating pattern surrounds the semi-conductor material layer to delineate a first active area and it penetrates partially into the support layer to delineate the first portion. An electrically conducting contact passes through the insulating pattern from a first lateral surface in contact with the counter-electrode through to a second surface. The contact is electrically connected to the counter-electrode.
    Type: Application
    Filed: April 4, 2012
    Publication date: October 11, 2012
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Maud VINET, Laurent GRENOUILLET, Yannick LE TIEC, Nicolas POSSEME
  • Publication number: 20120187488
    Abstract: A field effect device comprises a substrate of semiconductor on insulator type successively provided with a support substrate, an electrically insulating layer and a semiconductor material film. First and second source/drain electrodes are formed in the semiconductor material layer. A conduction channel is formed in the semiconductor material layer and separates the first and second source/drain electrodes. A counter-electrode is formed in the support substrate and faces the first and second source/drain electrodes and the conduction channel. The counter-electrode is formed by a doped area of the support substrate having a first doping impurity concentration which decreases from an interface between the electrically insulating layer and the support substrate.
    Type: Application
    Filed: January 18, 2012
    Publication date: July 26, 2012
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Laurent GRENOUILLET, Maud VINET
  • Publication number: 20120190214
    Abstract: The field effect device is formed on a substrate of semiconductor on insulator type provided with a support substrate separated from a semiconductor film by an electrically insulating layer. The source and drain electrodes are formed in the semiconductor film on each side of the gate electrode. The electrically insulating layer comprises a first area having a first electric capacitance value between the semiconductor film and the support substrate facing the gate electrode. The electrically insulating layer comprises second and third areas having a higher electric capacitance value than the first value between the semiconductor film and the support substrate facing the source and drain electrodes.
    Type: Application
    Filed: January 24, 2012
    Publication date: July 26, 2012
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Maud Vinet, Laurent Grenouillet, Yannick Le Tiec, Nicolas Posseme
  • Publication number: 20120187489
    Abstract: The field effect device comprises a sacrificial gate electrode having side walls covered by lateral spacers formed on a semiconductor material film. The source/drain electrodes are formed in the semiconductor material film and are arranged on each side of the gate electrode. A diffusion barrier element is implanted through the void left by the sacrificial gate so as to form a modified diffusion area underneath the lateral spacers. The modified diffusion area is an area where the mobility of the doping impurities is reduced compared with the source/drain electrodes.
    Type: Application
    Filed: January 24, 2012
    Publication date: July 26, 2012
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Laurent GRENOUILLET, Yannick LE TIEC, Nicolas POSSEME, Maud VINET
  • Publication number: 20120063717
    Abstract: Method of producing a photonic device including at least one light source and at least one photodetector on a structure including a waveguide layer, this method comprising the following steps: a) growing successively on a substrate (10), a photodetection structure (11) and a light source structure (12), the photodetection structure and the light source structure being made of a stack of layers, the light source layers being stacked on top of the photodetector layers and both structures sharing one of these layers.
    Type: Application
    Filed: February 1, 2010
    Publication date: March 15, 2012
    Applicants: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Laurent Grenouillet, Jean-Marc Fedeli, Liu Liu, Regis Orobtchouk, Philippe Regreny, Gunther Roelkens, Pedro Rojo-Romeo, Dries Van Thourhout
  • Publication number: 20110180776
    Abstract: The invention relates to a method for making optoelectronic devices comprising nanowire semiconductors, in which: the nanowires (2) are formed on a substrate (1), said nanowires being capable of emitting a light beam; a first electric contact area is formed at the substrate, and a second electric contact area is formed at the nanowires, characterised in that the second electric contact area is formed on the edge of the nanowires (2) in direct contact with said nanowires, on a predetermined height (h) thereof and in the vicinity of their end opposite the substrate, as well as between said nanowires, the upper surface (20) of the nanowires being exposed.
    Type: Application
    Filed: October 22, 2008
    Publication date: July 28, 2011
    Applicant: Commissariat AL'Energie Atomique ET Aux Energies Alternatives
    Inventors: Philippe Gilet, Laurent Grenouillet
  • Publication number: 20110150024
    Abstract: A method for introducing light into a waveguide formed on the upper surface of a microelectronics substrate, by means of a distributed feedback laser device formed by the association of an SOI-type structure having a portion forming said waveguide, of a stack of III-V semiconductor gain materials partially covering the waveguide, and of an optical grating, wherein the grating step is selected so that the optical power of the laser beam circulates in a loop from the III-V stack to the waveguide.
    Type: Application
    Filed: December 21, 2010
    Publication date: June 23, 2011
    Applicant: Commissariat A L'Energie Atomique et Aux Energies Alternatives
    Inventors: Tiphaine Dupont, Laurent Grenouillet
  • Patent number: 7691735
    Abstract: The invention relates to a method for manufacturing chips composed of at least one electrically conductive material. Such a method comprises the following steps: deposition, on a support, of an alloy comprising at least the electrically conductive material and a second material; exposure of the alloy to plasma etching, in order to cause the desorption of the materials of the alloy not forming part of the composition of the chips, that is at least the second material but not the electrically conductive material; formation of chips composed of at least said electrically conductive material.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: April 6, 2010
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Laurent Grenouillet, Jonathan Garcia, François Marion, Nicolas Olivier, Marion Perrin
  • Publication number: 20090162657
    Abstract: The invention relates to a method for manufacturing chips composed of at least one electrically conductive material. Such a method comprises the following steps: deposition, on a support, of an alloy comprising at least the electrically conductive material and a second material; exposure of the alloy to plasma etching, in order to cause the desorption of the materials of the alloy not forming part of the composition of the chips, that is at least the second material but not the electrically conductive material; formation of chips composed of at least said electrically conductive material.
    Type: Application
    Filed: October 20, 2008
    Publication date: June 25, 2009
    Applicant: Commissariat a L'Energie Atomique
    Inventors: Laurent Grenouillet, Jonathan Garcia, Francois Marion, Nicolas Olivier, Marion Perrin