Patents by Inventor Laurent Lefebvre

Laurent Lefebvre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11562459
    Abstract: A graphics pipeline includes a cache having cache lines that are configured to store data used to process frames in a graphics pipeline. The graphics pipeline is implemented using a processor that processes frames for the graphics pipeline using data stored in the cache. The processor processes a first frame and writes back a dirty cache line from the cache to a memory concurrently with processing of the first frame. The dirty cache line is retained in the cache and marked as clean subsequent to being written back to the memory. In some cases, the processor generates a hint that indicates a priority for writing back the dirty cache line based on a read command occupancy at a system memory controller.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: January 24, 2023
    Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Noor Mohammed Saleem Bijapur, Ashish Khandelwal, Laurent Lefebvre, Anirudh R. Acharya
  • Patent number: 11551398
    Abstract: Systems, apparatuses, and methods for implementing light volume rendering techniques are disclosed. A processor is coupled to a memory. A processor renders the geometry of a scene into a geometry buffer. For a given light source in the scene, the processor initiates two shader pipeline passes to determine which pixels in the geometry buffer to light. On the first pass, the processor renders a front-side of a light volume corresponding to the light source. Any pixels of the geometry buffer which are in front of the front-side of the light volume are marked as pixels to be discarded. Then, during the second pass, only those pixels which were not marked to be discarded are sent to the pixel shader. This approach helps to reduce the overhead involved in applying a lighting effect to the scene by reducing the amount of work performed by the pixel shader.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: January 10, 2023
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Mika Tuomi, Miikka Petteri Kangasluoma, Jan Henrik Achrenius, Laurent Lefebvre
  • Publication number: 20220277508
    Abstract: A method, computer system, and a non-transitory computer-readable storage medium for performing primitive batch binning are disclosed. The method, computer system, and non-transitory computer-readable storage medium include techniques for generating a primitive batch from a plurality of primitives, computing respective bin intercepts for each of the plurality of primitives in the primitive batch, and shading the primitive batch by iteratively processing each of the respective bin intercepts computed until all of the respective bin intercepts are processed.
    Type: Application
    Filed: May 16, 2022
    Publication date: September 1, 2022
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Michael Mantor, Laurent Lefebvre, Mark Fowler, Timothy Kelley, Mikko Alho, Mika Tuomi, Kiia Kallio, Patrick Klas Rudolf Buss, Jari Antero Komppa, Kaj Tuomi
  • Publication number: 20220261947
    Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.
    Type: Application
    Filed: May 3, 2022
    Publication date: August 18, 2022
    Inventors: Laurent LEFEBVRE, Andrew GRUBER, Stephen MOREIN
  • Publication number: 20220222770
    Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.
    Type: Application
    Filed: March 30, 2022
    Publication date: July 14, 2022
    Inventors: Stephen L. MOREIN, Laurent LEFEBVRE, Andrew E. GRUBER, Andi SKENDE
  • Patent number: 11379941
    Abstract: Improvements in the graphics processing pipeline are disclosed. More specifically, a new primitive shader stage performs tasks of the vertex shader stage or a domain shader stage if tessellation is enabled, a geometry shader if enabled, and a fixed function primitive assembler. The primitive shader stage is compiled by a driver from user-provided vertex or domain shader code, geometry shader code, and from code that performs functions of the primitive assembler. Moving tasks of the fixed function primitive assembler to a primitive shader that executes in programmable hardware provides many benefits, such as removal of a fixed function crossbar, removal of dedicated parameter and position buffers that are unusable in general compute mode, and other benefits.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: July 5, 2022
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Todd Martin, Mangesh P. Nijasure, Randy W. Ramsey, Michael Mantor, Laurent Lefebvre
  • Patent number: 11361399
    Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: June 14, 2022
    Assignee: ATI Technologies ULC
    Inventors: Laurent Lefebvre, Andrew Gruber, Stephen Morein
  • Patent number: 11335052
    Abstract: A system, method and a non-transitory computer readable storage medium are provided for hybrid rendering with deferred primitive batch binning. A primitive batch is generated from one or more primitives. A bin is identified for processing the primitive batch. At least a portion of each primitive intersecting the identified bin is processed and a next bin for processing the primitive batch is identified based on an intercept walk order. The processing is iteratively repeated for the one or more primitives in the primitive batch for successive bins until all primitives of the primitive batch are completely processed. Then, the one or more primitives in the primitive batch are further processed.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: May 17, 2022
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Michael Mantor, Laurent Lefebvre, Mark Fowler, Timothy Kelley, Mikko Alho, Mika Tuomi, Kiia Kallio, Patrick Klas Rudolf Buss, Jari Antero Komppa, Kaj Tuomi
  • Patent number: 11328382
    Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: May 10, 2022
    Assignee: ATI Technologies ULC
    Inventors: Stephen L. Morein, Laurent Lefebvre, Andrew E. Gruber, Andi Skende
  • Patent number: 11308648
    Abstract: Sampling circuitry independently accesses channels of texture data that represent a set of pixels. One or more processing units separately compress the channels of the texture data and store compressed data representative of the channels of the texture data for the set of pixels. The channels can include a red channel, a blue channel, and a green channel that represent color values of the set of pixels and an alpha channel that represents degrees of transparency of the set of pixels. Storing the compressed data can include writing the compress data to portions of a cache. The processing units can identify a subset of the set of pixels that share a value of a first channel of the plurality of channels and represent the value of the first channel over the subset of the set of pixels using information representing the value, the first channel, and boundaries of the subset.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: April 19, 2022
    Assignees: Advanced Micro Devices, Inc., ATI TECHNOLOGIES ULC
    Inventors: Saurabh Sharma, Laurent Lefebvre, Sagar Shankar Bhandare, Ruijin Wu
  • Publication number: 20220092826
    Abstract: Sampling circuitry independently accesses channels of texture data that represent a set of pixels. One or more processing units separately compress the channels of the texture data and store compressed data representative of the channels of the texture data for the set of pixels. The channels can include a red channel, a blue channel, and a green channel that represent color values of the set of pixels and an alpha channel that represents degrees of transparency of the set of pixels. Storing the compressed data can include writing the compress data to portions of a cache. The processing units can identify a subset of the set of pixels that share a value of a first channel of the plurality of channels and represent the value of the first channel over the subset of the set of pixels using information representing the value, the first channel, and boundaries of the subset.
    Type: Application
    Filed: September 23, 2020
    Publication date: March 24, 2022
    Inventors: Saurabh SHARMA, Laurent LEFEBVRE, Sagar Shankar BHANDARE, Ruijin WU
  • Publication number: 20220092801
    Abstract: Systems, apparatuses, and methods for implementing a depth buffer pre-pass are disclosed. A rendering application uses a binning approach to render primitives of a virtual scene on a tile-by-tile basis, with each tile corresponding to a portion of the screen. The application causes a depth buffer pre-pass to be performed for the primitives of the tile before a pixel shader is invoked. During the depth buffer pre-pass, only the depth part of the virtual scene is rendered to determine which pixel samples are visible and which pixel samples are hidden. Then, the scene is redrawn, but the pixel samples that are hidden are not sent to the pixel shader. In cases where a relatively large percentage of primitives overlap, this technique increases the efficiency of the rendering application since pixel shading can be avoided for the pixel samples that are hidden.
    Type: Application
    Filed: September 24, 2020
    Publication date: March 24, 2022
    Inventors: Jan Henrik Achrenius, Mika Tuomi, Kiia Kallio, Pazhani Pillai, Laurent Lefebvre
  • Publication number: 20210398242
    Abstract: A graphics pipeline includes a cache having cache lines that are configured to store data used to process frames in a graphics pipeline. The graphics pipeline is implemented using a processor that processes frames for the graphics pipeline using data stored in the cache. The processor processes a first frame and writes back a dirty cache line from the cache to a memory concurrently with processing of the first frame. The dirty cache line is retained in the cache and marked as clean subsequent to being written back to the memory. In some cases, the processor generates a hint that indicates a priority for writing back the dirty cache line based on a read command occupancy at a system memory controller.
    Type: Application
    Filed: December 21, 2020
    Publication date: December 23, 2021
    Inventors: Noor Mohammed Saleem BIJAPUR, Ashish KHANDELWAL, Laurent LEFEBVRE, Anirudh R. ACHARYA
  • Publication number: 20210233205
    Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.
    Type: Application
    Filed: April 14, 2021
    Publication date: July 29, 2021
    Inventors: Stephen L. MOREIN, Laurent LEFEBVRE, Andrew E. GRUBER, Andi SKENDE
  • Publication number: 20210209831
    Abstract: A method, system, and non-transitory computer readable storage medium for rasterizing primitives are disclosed. The method, system, and non-transitory computer readable storage medium includes: generating a primitive batch from a sequence of one or more primitives, wherein the primitive batch includes primitives sorted into one or more row groups based on which row of a plurality of rows each primitive intersects; and processing each row group, the processing for each row group including: identifying one or more primitive column intercepts for each of the one or more primitives in the row group, wherein each combination of primitive column intercept and row identifies a bin; and rasterizing the one or more primitives that intersect the bin.
    Type: Application
    Filed: March 22, 2021
    Publication date: July 8, 2021
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Michael Mantor, Laurent Lefebvre, Mikko Alho, Mika Tuomi, Kiia Kallio
  • Patent number: 11023996
    Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: June 1, 2021
    Assignee: ATI Technologies ULC
    Inventors: Stephen L. Morein, Laurent Lefebvre, Andrew E. Gruber, Andi Skende
  • Publication number: 20210158473
    Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.
    Type: Application
    Filed: February 4, 2021
    Publication date: May 27, 2021
    Inventors: Laurent Lefebvre, Andrew Gruber, Stephen Morein
  • Publication number: 20210150797
    Abstract: Systems, apparatuses, and methods for implementing light volume rendering techniques are disclosed. A processor is coupled to a memory. A processor renders the geometry of a scene into a geometry buffer. For a given light source in the scene, the processor initiates two shader pipeline passes to determine which pixels in the geometry buffer to light. On the first pass, the processor renders a front-side of a light volume corresponding to the light source. Any pixels of the geometry buffer which are in front of the front-side of the light volume are marked as pixels to be discarded. Then, during the second pass, only those pixels which were not marked to be discarded are sent to the pixel shader. This approach helps to reduce the overhead involved in applying a lighting effect to the scene by reducing the amount of work performed by the pixel shader.
    Type: Application
    Filed: August 31, 2020
    Publication date: May 20, 2021
    Inventors: Mika Tuomi, Miikka Petteri Kangasluoma, Jan Henrik Achrenius, Laurent Lefebvre
  • Patent number: 10957007
    Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: March 23, 2021
    Assignee: ATI Technologies ULC
    Inventors: Laurent Lefebvre, Andrew Gruber, Stephen Morein
  • Patent number: 10957094
    Abstract: A system, method and a computer program product are provided for hybrid rendering with deferred primitive batch binning A primitive batch is generated from a sequence of primitives. Initial bin intercepts are identified for primitives in the primitive batch. A bin for processing is identified. The bin corresponds to a region of a screen space. Pixels of the primitives intercepting the identified bin are processed. Next bin intercepts are identified while the primitives intercepting the identified bin are processed.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: March 23, 2021
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Michael Mantor, Laurent Lefebvre, Mikko Alho, Mika Tuomi, Kiia Kallio