Patents by Inventor Laurent Lefebvre
Laurent Lefebvre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180276790Abstract: An apparatus, such as a head mounted device (HMD), includes one or more processors configured to implement a graphics pipeline that renders pixels in window space with a nonuniform pixel spacing. The apparatus also includes a first distortion function that maps the non-uniformly spaced pixels in window space to uniformly spaced pixels in raster space. The apparatus further includes a scan converter configured to sample the pixels in window space through the first distortion function. The scan converter is configured to render display pixels used to generate an image for display to a user based on the uniformly spaced pixels in raster space. In some cases, the pixels in the window space are rendered such that a pixel density per subtended area is constant across the user's field of view.Type: ApplicationFiled: December 15, 2017Publication date: September 27, 2018Inventors: Michael MANTOR, Laurent LEFEBVRE, Mika TUOMI, Kiia KALLIO
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Publication number: 20180182060Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.Type: ApplicationFiled: February 21, 2018Publication date: June 28, 2018Inventors: Laurent Lefebvre, Andrew Gruber, Stephen Morein
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Publication number: 20180165872Abstract: Techniques for removing or identifying overlapping fragments in a fragment stream after z-culling are disclosed. The techniques include maintaining a first-in-first-out buffer that stores post-z-cull fragments. Each time a new fragment is received at the buffer, the screen position of the fragment is checked against all other fragments in the buffer. If the screen position of the fragment matches the screen position of a fragment in the buffer, then the fragment in the buffer is removed or marked as overlapping. If the screen position of the fragment does not match the screen position of any fragment in the buffer, then no modification is performed to fragments already in the buffer. In either case, he fragment is added to the buffer. The contents of the buffer are transmitted to the pixel shader for pixel shading at a later time.Type: ApplicationFiled: December 9, 2016Publication date: June 14, 2018Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Laurent Lefebvre, Michael Mantor, Mark Fowler, Mikko Alho, Mika Tuomi, Kiia Kallio, Patrick Klas Rudolf Buss, Jari Antero Komppa, Kaj Tuomi, Christopher J. Brennan
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Publication number: 20180082399Abstract: Improvements in the graphics processing pipeline are disclosed. More specifically, a new primitive shader stage performs tasks of the vertex shader stage or a domain shader stage if tessellation is enabled, a geometry shader if enabled, and a fixed function primitive assembler. The primitive shader stage is compiled by a driver from user-provided vertex or domain shader code, geometry shader code, and from code that performs functions of the primitive assembler. Moving tasks of the fixed function primitive assembler to a primitive shader that executes in programmable hardware provides many benefits, such as removal of a fixed function crossbar, removal of dedicated parameter and position buffers that are unusable in general compute mode, and other benefits.Type: ApplicationFiled: January 25, 2017Publication date: March 22, 2018Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Todd Martin, Mangesh P. Nijasure, Randy W. Ramsey, Michael Mantor, Laurent Lefebvre
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Patent number: 9922395Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.Type: GrantFiled: January 26, 2016Date of Patent: March 20, 2018Assignee: ATI TECHNOLOGIES ULCInventors: Laurent Lefebvre, Andrew Gruber, Stephen Morein
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Patent number: 9904970Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.Type: GrantFiled: June 9, 2014Date of Patent: February 27, 2018Assignee: ATI Technologies ULCInventors: Laurent Lefebvre, Andrew Gruber, Stephen Morein
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Patent number: 9896894Abstract: A drilling and grouting device comprises a drill string including a hollow elongate outer rod having a central axis and a hollow elongate inner rod located coaxially within said outer rod, wherein a first outer flow path is defined between said inner and outer rod, and a first central flow path is defined inside said inner rod, a drill bit aligned with said inner rod along said central axis and including a second central flow path, and a crossover part interposed between said inner rod and said drill bit along said central axis, which is configured to connect the first central flow path with a second outer flow path surrounding the drill bit to form a main path and to connect said first outer flow path with said second central flow path to form a secondary path. Also disclosed are systems and methods that include and use the device.Type: GrantFiled: December 21, 2012Date of Patent: February 20, 2018Assignee: SOLETANCHE FREYSSINETInventors: Luca Barison, Larry Goff, Laurent Lefebvre, Steve England, Stefano Gabaldo, Michael Justason
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Patent number: 9582846Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.Type: GrantFiled: February 5, 2015Date of Patent: February 28, 2017Assignee: ATI TECHNOLOGIES ULCInventors: Stephen L. Morein, Laurent Lefebvre, Andrew E. Gruber, Andi Skende
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Publication number: 20160371873Abstract: A system, method and a computer program product are provided for hybrid rendering with deferred primitive batch binning A primitive batch is generated from a sequence of primitives. Initial bin intercepts are identified for primitives in the primitive batch. A bin for processing is identified. The bin corresponds to a region of a screen space. Pixels of the primitives intercepting the identified bin are processed. Next bin intercepts are identified while the primitives intercepting the identified bin are processed.Type: ApplicationFiled: August 29, 2016Publication date: December 22, 2016Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Michael Mantor, Laurent Lefebvre, Mikko Alho, Mika Tuomi, Kiia Kallio
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Publication number: 20160307356Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.Type: ApplicationFiled: June 27, 2016Publication date: October 20, 2016Inventors: Stephen L. Morein, Laurent Lefebvre, Andrew E. Gruber, Andi Skende
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Publication number: 20160140687Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.Type: ApplicationFiled: January 26, 2016Publication date: May 19, 2016Inventors: Laurent Lefebvre, Andrew Gruber, Stephen Morein
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Patent number: 9304772Abstract: A system and method is provided for improving efficiency, power, and bandwidth consumption in parallel processing. Rather than requiring memory polling to ensure ordered execution of processes or threads in wavefronts, the techniques disclosed herein provide a system and method to allow any process or thread in a wavefront to run out of order as long as needed, but ensure ordered execution of multiple ordered instructions when needed. These operations are handled efficiently in hardware, but are flexible enough to be implemented in all manner of programming models.Type: GrantFiled: March 29, 2012Date of Patent: April 5, 2016Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Laurent Lefebvre, Michael Mantor
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Publication number: 20150252639Abstract: A drilling and grouting device comprises a drill string including a hollow elongate outer rod having a central axis and a hollow elongate inner rod located coaxially within said outer rod, wherein a first outer flow path is defined between said inner and outer rod, and a first central flow path is defined inside said inner rod, a drill bit aligned with said inner rod along said central axis and including a second central flow path, and a crossover part interposed between said inner rod and said drill bit along said central axis, which is configured to connect the first central flow path with a second outer flow path surrounding the drill bit to form a main path and to connect said first outer flow path with said second central flow path to form a secondary path. Also disclosed are systems and methods that include and use the device.Type: ApplicationFiled: December 21, 2012Publication date: September 10, 2015Inventors: Luca Barison, Larry Goff, Laurent Lefebvre, Steve England, Stefano Gabaldo, Michael Justason
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Publication number: 20150154731Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.Type: ApplicationFiled: February 5, 2015Publication date: June 4, 2015Inventors: Stephen L. Morein, Laurent Lefebvre, Andrew E. Gruber, Andi Skende
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Patent number: 8972693Abstract: A system and method is provided for improving efficiency, power, and bandwidth consumption in parallel processing. Rather than using memory polling to ensure that enough space is available in memory locations for, for example, write instructions, the techniques disclosed herein provide a system and method to automate this evaluation mechanism in environments such as data-parallel processing to efficiently check available space in memory locations before instructions such as write threads are allowed. These operations are handled efficiently in hardware, but are flexible enough to be implemented in all manner of programming models.Type: GrantFiled: March 29, 2012Date of Patent: March 3, 2015Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Laurent Lefebvre, Michael Mantor
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Publication number: 20140300613Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.Type: ApplicationFiled: June 23, 2014Publication date: October 9, 2014Inventors: Stephen L. Morein, Laurent Lefebvre, Andrew E. Gruber, Andi Skende
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Publication number: 20140292784Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.Type: ApplicationFiled: June 9, 2014Publication date: October 2, 2014Inventors: Laurent Lefebvre, Andrew Gruber, Stephen Morein
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Publication number: 20140292756Abstract: A system, method and a computer program product are provided for hybrid rendering with deferred primitive batch binning. A primitive batch is generated from a sequence of primitives. Initial bin intercepts are identified for primitives in the primitive batch. A bin for processing is identified. The bin corresponds to a region of a screen space. Pixels of the primitives intercepting the identified bin are processed. Next bin intercepts are identified while the primitives intercepting the identified bin are processed.Type: ApplicationFiled: March 29, 2013Publication date: October 2, 2014Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Michael MANTOR, Laurent Lefebvre, Mark Fowler, Timothy Kelley, Mikko Alho, Mika Tuomi, Kallio Kia, Patrick Klas Rudolf Buss, Jari Antero Komppa, Kaj Tuomi
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Patent number: 8760454Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data b a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.Type: GrantFiled: May 17, 2011Date of Patent: June 24, 2014Assignee: ATI Technologies ULCInventors: Stephen L. Morein, Laurent Lefebvre, Andrew E. Gruber, Andi Skende
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Patent number: 8749563Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.Type: GrantFiled: March 18, 2013Date of Patent: June 10, 2014Assignee: ATI Technologies ULCInventors: Laurent Lefebvre, Andrew Gruber, Stephen Morein