Patents by Inventor Laurent Lefebvre
Laurent Lefebvre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130262812Abstract: A system and method is provided for improving efficiency, power, and bandwidth consumption in parallel processing. Rather than using memory polling to ensure that enough space is available in memory locations for, for example, write instructions, the techniques disclosed herein provide a system and method to automate this evaluation mechanism in environments such as data-parallel processing to efficiently check available space in memory locations before instructions such as write threads are allowed. These operations are handled efficiently in hardware, but are flexible enough to be implemented in all manner of programming models.Type: ApplicationFiled: March 29, 2012Publication date: October 3, 2013Inventors: Laurent Lefebvre, Michael Mantor
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Publication number: 20130262834Abstract: A system and method is provided for improving efficiency, power, and bandwidth consumption in parallel processing. Rather than requiring memory polling to ensure ordered execution of processes or threads, the techniques disclosed herein provide a system and method to allow any process or thread to run out of order as long as needed, but ensure ordered execution of multiple ordered instructions when needed. These operations are handled efficiently in hardware, but are flexible enough to be implemented in all manner of programming models.Type: ApplicationFiled: March 29, 2012Publication date: October 3, 2013Inventors: Laurent Lefebvre, Michael Mantor
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Patent number: 8468547Abstract: Systems and methods for synchronizing thread wavefronts and associated events are disclosed. According to an embodiment, a method for synchronizing one or more thread wavefronts and associated events includes inserting a first event associated with a first data output from a first thread wavefront into an event synchronizer. The event synchronizer is configured to release the first event before releasing events inserted subsequent to the first event. The method further includes releasing the first event from the event synchronizer after the first data is stored in the memory. Corresponding system and computer readable medium embodiments are also disclosed.Type: GrantFiled: November 23, 2010Date of Patent: June 18, 2013Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Laurent LeFebvre, Michael Mantor, Deborah Lynne Szasz
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Patent number: 8400459Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.Type: GrantFiled: May 9, 2007Date of Patent: March 19, 2013Assignee: ATI Technologies ULCInventors: Laurent Lefebvre, Andrew E. Gruber, Stephen L. Morein
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Patent number: 8305382Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a command thread from either the plurality of pixel or vertex command threads based on relative priorities of the plurality of pixel command threads and the plurality of vertex command threads. The selected command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.Type: GrantFiled: October 5, 2011Date of Patent: November 6, 2012Assignee: ATI Technologies ULCInventors: Laurent Lefebvre, Andrew Gruber, Stephen Morein
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Patent number: 8190826Abstract: Systems and methods for pipelined synchronization in a write-combining cache are described herein. An embodiment to transmit data to a memory to enable pipelined synchronization of a cache includes obtaining a plurality of synchronization events for transactions with said memory, calculating one or more matches between said events and said data stored in one or more cache-lines of said cache, storing event time stamps of events associated with said matches, generating one or more priority values based on said event time stamps, concurrently transmitting said data to said memory based on said priority values.Type: GrantFiled: May 28, 2008Date of Patent: May 29, 2012Assignee: Advanced Micro Devices, Inc.Inventors: Laurent Lefebvre, Michael Mantor, Robert Hankinson
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Publication number: 20120131596Abstract: Systems and methods for synchronizing thread wavefronts and associated events are disclosed. According to an embodiment, a method for synchronizing one or more thread wavefronts and associated events includes inserting a first event associated with a first data output from a first thread wavefront into an event synchronizer. The event synchronizer is configured to release the first event before releasing events inserted subsequent to the first event. The method further includes releasing the first event from the event synchronizer after the first data is stored in the memory. Corresponding system and computer readable medium embodiments are also disclosed.Type: ApplicationFiled: November 23, 2010Publication date: May 24, 2012Applicants: Advance Micro Devices, Inc., ATI Technologies ULCInventors: Laurent LEFEBVRE, Michael Mantor, Deborah Lynne Szasz
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Publication number: 20120110309Abstract: Methods, systems, and computer readable media for improved transfer of processing data outputs to memory are disclosed. According to an embodiment, a method for transferring outputs of a plurality of threads concurrently executing in one or more processing units to a memory includes: forming, based upon one or more of the outputs, a combined memory export instruction comprising one or more data elements and one or more control elements; and sending the combined memory export instruction to the memory. The combined memory export instruction can be sent to memory in a single clock cycle. Another method includes: forming, based upon outputs from two or more of the threads, a memory export instruction comprising two or more data elements; embedding at least one address representative of the two or more of the outputs in a second memory instruction; and sending the memory export instruction and the second memory instruction to the memory.Type: ApplicationFiled: October 29, 2010Publication date: May 3, 2012Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Laurent Lefebvre, Michael Mantor, Robert Hankinson
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Publication number: 20120019543Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a command thread from either the plurality of pixel or vertex command threads based on relative priorities of the plurality of pixel command threads and the plurality of vertex command threads. The selected command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.Type: ApplicationFiled: October 5, 2011Publication date: January 26, 2012Applicant: ATI Technologies ULCInventors: Laurent Lefebvre, Andrew E. Gruber, Stephen L. Morein
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Patent number: 8072461Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a command thread from either the plurality of pixel or vertex command threads based on relative priorities of the plurality of pixel command threads and the plurality of vertex command threads. The selected command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.Type: GrantFiled: March 5, 2010Date of Patent: December 6, 2011Assignee: ATI Technologies ULCInventors: Laurent Lefebvre, Andrew Gruber, Stephen Morein
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Publication number: 20110216077Abstract: A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.Type: ApplicationFiled: May 17, 2011Publication date: September 8, 2011Applicant: ATI TECHNOLOGIES ULCInventors: Stephen Morein, Laurent Lefebvre, Andy Gruber, Andi Skende
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Publication number: 20100231592Abstract: A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.Type: ApplicationFiled: June 1, 2010Publication date: September 16, 2010Applicant: ATI Technologies ULCInventors: Steven Morein, Laurent Lefebvre, Andy Gruber, Andi Skende
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Patent number: 7746348Abstract: A graphics processing system comprises a command processing engine capable of processing pixel command threads and vertex command threads. The command processing engine is coupled to both a renderer and a scan converter. Upon completing processing of a command thread, which may comprise a pixel command thread or a vertex command thread, the command engine provides the command thread to either the renderer or the scan converter.Type: GrantFiled: May 9, 2007Date of Patent: June 29, 2010Assignee: ATI Technologies ULCInventors: Laurent Lefebvre, Andrew E. Gruber, Stephen L. Morein
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Publication number: 20100156915Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a command thread from either the plurality of pixel or vertex command threads based on relative priorities of the plurality of pixel command threads and the plurality of vertex command threads. The selected command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.Type: ApplicationFiled: March 5, 2010Publication date: June 24, 2010Applicant: ATI TECHNOLOGIES ULCInventors: Laurent LEFEBVRE, Andrew E. GRUBER, Stephen L. MOREIN
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Patent number: 7742053Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a command thread from either the plurality of pixel or vertex command threads based on relative priorities of the plurality of pixel command threads and the plurality of vertex command threads. The selected command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.Type: GrantFiled: May 9, 2007Date of Patent: June 22, 2010Assignee: ATI Technologies ULCInventors: Laurent Lefebvre, Andrew E. Gruber, Stephen L. Morein
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Patent number: 7656417Abstract: A method for determining the appearance of a pixel includes receiving fragment data for a pixel to be rendered; storing the fragment data; and determining an appearance value for the pixel based on the stored fragment data, wherein a portion of the stored fragment data is dropped when the number of fragment data per pixel exceeds a threshold value enabling large savings in memory footprint without impacting perceivably on the image quality. A graphics processor includes a rasterizer operative to generate fragment data for a pixel to be rendered in response to primitive information; and a render back end circuit, coupled to the rasterizer, operative to determine a pixel appearance value based on the fragment data by dropping the fragment data having the least effect on pixel appearance.Type: GrantFiled: February 12, 2004Date of Patent: February 2, 2010Assignee: ATI Technologies ULCInventors: Larry D. Seiler, Laurent Lefebvre
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Patent number: 7636095Abstract: A method for rendering an object including receiving a pixel tile representing a portion of a primitive to be rendered, determining attributes of a reference pixel within the pixel tile, and determining the attributes of neighboring pixels within the pixel tile based on barycentric differences relative to the reference pixel is disclosed. A circuit for calculating at least one attribute of an object to be rendered includes an initial calculation circuit providing full precision reference pixel attribute data in response to a pixel tile that defines at least a portion of the object; and a derivative circuit, operatively coupled to the initial calculation circuit, providing reduced precision neighboring pixel attribute data in response to the pixel tile. The derivative circuit includes a plurality of pixel attribute sub-circuits or components, which determine the attribute values of neighboring pixels within the pixel tile at a precision less than that of the precision used to define the reference pixel.Type: GrantFiled: September 6, 2002Date of Patent: December 22, 2009Assignee: ATI Technologies, Inc.Inventors: Laurent Lefebvre, Stephen L. Morein, Jay C. Wilkinson
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Publication number: 20090300288Abstract: Systems and methods for pipelined synchronization in a write-combining cache are described herein. An embodiment to transmit data to a memory to enable pipelined synchronization of a cache includes obtaining a plurality of synchronization events for transactions with said memory, calculating one or more matches between said events and said data stored in one or more cache-lines of said cache, storing event time stamps of events associated with said matches, generating one or more priority values based on said event time stamps, concurrently transmitting said data to said memory based on said priority values.Type: ApplicationFiled: May 28, 2008Publication date: December 3, 2009Inventors: Laurent LEFEBVRE, Michael Mantor, Robert Hankinson
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Patent number: 7538765Abstract: A method and apparatus for generating hierarchical depth culling characteristics includes determining a first minimum depth value and a first maximum depth value for a first graphical element. The graphical element may be a primitive. The first minimum depth value may be a minimum Z-plane depth of a pixel within the primitive and a first maximum depth value is a maximum Z-plane value for a pixel within the primitive. The method and apparatus further includes determining a second minimum depth value and a second maximum depth value for a second graphical element, which may be a tile. The method and apparatus further includes calculating an intersection depth range having an intersection minimum depth value and an intersection maximum depth value based on the intersection of the first minimum depth value and the first maximum depth value and the second minimum depth value and the second maximum depth value.Type: GrantFiled: August 10, 2004Date of Patent: May 26, 2009Assignee: ATI International SRLInventors: Larry D. Seiler, Laurent Lefebvre, Stephen L. Morein
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Patent number: 7336275Abstract: A pseudo random number generator that generates a plurality of intermediate values, where each successive intermediate value is based, at least in part, on one of the succeeding intermediate values, where a final value based on a subset of the plurality of intermediate values. In application, the final value is based on performing a logical operation on the penultimate and last generated intermediate values.Type: GrantFiled: September 6, 2002Date of Patent: February 26, 2008Assignee: ATI Technologies Inc.Inventors: Laurent Lefebvre, Stephen L. Morein