Abstract: A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.

Abstract: A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.

Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a command thread from either the plurality of pixel or vertex command threads based on relative priorities of the plurality of pixel command threads and the plurality of vertex command threads. The selected command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

Abstract: A graphics processing system comprises a command processing engine capable of processing pixel command threads and vertex command threads. The command processing engine is coupled to both a renderer and a scan converter. Upon completing processing of a command thread, which may comprise a pixel command thread or a vertex command thread, the command engine provides the command thread to either the renderer or the scan converter.

Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

Abstract: The present invention includes a multi-thread graphics processing system and method thereof including a reservation station having a plurality of command threads stored therein. The system and method further includes an arbiter operably coupled to the reservation station such that the arbiter retrieves a first command thread of the plurality of command threads stored therein such that the arbiter receives the command thread and thereupon provides the command thread to a command processing engine. The system and method further includes the command processing engine coupled to receive the first command thread from the arbiter such that the command processor may perform at least one processing command from the command thread. Whereupon, a command processing engine provides the first command thread back to the associated reservation station.

Abstract: Composition based on a crosslinkable polyethylene comprising from 0.05 to 0.24 hydrolysable silane groups per 100 —CH2— units and having a standard density SD of at least 954 kg/m3 and a melt flow index MI5 of less than 1.5 g/10 min. Pipes for the transportation of fluids under pressure, which can be obtained by extruding this composition and then hydrolysing it.

Abstract: A method and apparatus for generating hierarchical depth culling characteristics includes determining a first minimum depth value and a first maximum depth value for a first graphical element. The graphical element may be a primitive. The first minimum depth value may be a minimum Z-plane depth of a pixel within the primitive and a first maximum depth value is a maximum Z-plane value for a pixel within the primitive. The method and apparatus further includes determining a second minimum depth value and a second maximum depth value for a second graphical element, which may be a tile. The method and apparatus further includes calculating an intersection depth range having an intersection minimum depth value and an intersection maximum depth value based on the intersection of the first minimum depth value and the first maximum depth value and the second minimum depth value and the second maximum depth value.

Abstract: A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.

Abstract: A method for determining the appearance of a pixel includes receiving fragment data for a pixel to be rendered; storing the fragment data; and determining an appearance value for the pixel based on the stored fragment data, wherein a portion of the stored fragment data is dropped when the number of fragment data per pixel exceeds a threshold value enabling large savings in memory footprint without impacting perceivably on the image quality. A graphics processor includes a rasterizer operative to generate fragment data for a pixel to be rendered in response to primitive information; and a render back end circuit, coupled to the rasterizer, operative to determine a pixel appearance value based on the fragment data by dropping the fragment data having the least effect on pixel appearance.

Abstract: A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.

Abstract: A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.

Abstract: The present invention includes a multi-thread graphics processing system and method thereof including a reservation station having a plurality of command threads stored therein. The system and method further includes an arbiter operably coupled to the reservation station such that the arbiter retrieves a first command thread of the plurality of command threads stored therein such that the arbiter receives the command thread and thereupon provides the command thread to a command processing engine. The system and method further includes the command processing engine coupled to receive the first command thread from the arbiter such that the command processor may perform at least one processing command from the command thread. Whereupon, a command processing engine provides the first command thread back to the associated reservation station.

Abstract: Composition based on a crosslinkable polyethylene comprising from 0.05 to 0.24 hydrolysable silane groups per 100 —CH2— units and having a standard density SD of at least 954 kg/m3 and a melt flow index MI5 of less than 1.5 g/10 min. Pipes for the transportation of fluids under pressure, which can be obtained by extruding this composition and then hydrolysing it.

Abstract: A method and corresponding apparatus for calculating the centroid of a fragment to be rendered is disclosed. The method calls for moving the sampling point of a pixel from its initial center point to the center of the fragment containing a portion of an image to be rendered. The method comprises the steps of receiving a coverage mask containing at least one sample point of the pixel fragment under consideration; determining which of the sample points are within the fragment; determining a value representative of the number of sample points that are within the fragment; determining offset values of the fragment centroid based on the number of sample points within the fragment; and determining the barycentric coordinates of the centroid of the fragment. The centroid of the fragment is where sampling of the primitive will occur. By sampling at the centroid of the fragment, rendered image quality is improved due to the reduced anti-aliasing effects at the edges of the primitive.

Abstract: A pseudo random number generator that generates a plurality of intermediate values, where each successive intermediate value is based, at least in part, on one of the succeeding intermediate values, where a final value based on a subset of the plurality of intermediate values. In application, the final value is based on performing a logical operation on the penultimate and last generated intermediate values.

Abstract: A rendering engine includes a pixel shader operative to provide pixel position information, a gradient noise engine, coupled to the pixel shader, operative to generate gradient noise data in response to the pixel data, and a shared memory, coupled to the gradient noise engine, operative to store recently generated gradient noise data, wherein the stored gradient noise data is combined with pixel position data to generate an appearance value for a pixel of interest.

Abstract: A method for rendering an object including receiving a pixel tile representing a portion of a primitive to be rendered, determining attributes of a reference pixel within the pixel tile, and determining the attributes of neighboring pixels within the pixel tile based on barycentric differences relative to the reference pixel is disclosed. A circuit for calculating at least one attribute of an object to be rendered includes an initial calculation circuit providing full precision reference pixel attribute data in response to a pixel tile that defines at least a portion of the object; and a derivative circuit, operatively coupled to the initial calculation circuit, providing reduced precision neighboring pixel attribute data in response to the pixel tile. The derivative circuit includes a plurality of pixel attribute sub-circuits or components, which determine the attribute values of neighboring pixels within the pixel tile at a precision less than that of the precision used to define the reference pixel.

Abstract: A method and corresponding apparatus for calculating the centroid of a fragment to be rendered is disclosed. The method calls for moving the sampling point of a pixel from its initial center point to the center of the fragment containing a portion of an image to be rendered. The method comprises the steps of receiving a coverage mask containing at least one sample point of the pixel fragment under consideration; determining which of the sample points are within the fragment; determining a value representative of the number of sample points that are within the fragment; determining offset values of the fragment centroid based on the number of sample points within the fragment; and determining the barycentric coordinates of the centroid of the fragment. The centroid of the fragment is where sampling of the primitive will occur. By sampling at the centroid of the fragment, rendered image quality is improved due to the reduced anti-aliasing effects at the edges of the primitive.