Patents by Inventor Lawrence A. Clevenger

Lawrence A. Clevenger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190155236
    Abstract: A computer-mediated physical damping feedback system includes a motion damping device, a voltage conversion controller, and a voltage generator controller. The motion damping device is worn by a participant present in a real-world environment, and is configured to vary a moveable flexibility of the participant in response to receiving an electrical voltage. The voltage conversion controller is in signal communication with a computer-mediated environment engine (CMEE) controller, and is configured to determine a voltage level of the electrical voltage based at least in part on the interaction between the participant and a computer-mediated environment. The voltage generator controller is in signal communication with the motion damping device and the voltage conversion controller. The voltage generator controller is configured to generate the electrical voltage at the voltage level that induces the stress applied by the motion damping device.
    Type: Application
    Filed: November 17, 2017
    Publication date: May 23, 2019
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Christopher J. Penny, Michael Rizzolo, Aldis Sipolins
  • Patent number: 10297750
    Abstract: A method is presented for forming a semiconductor device. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form a plurality of trenches for receiving a first conducting material, forming a resistive switching memory element over at least one trench of the plurality of trenches, the resistive switching memory element having a conducting cap formed thereon, and depositing a dielectric cap over the trenches. The method further includes etching portions of the insulating layer to expose a section of the dielectric cap formed over the resistive switching memory element, etching the exposed section of the dielectric cap to expose the conducting cap of the resistive switching memory element, and forming a barrier layer in direct contact with the exposed section of the conducting cap.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Chih-Chao Yang
  • Publication number: 20190148303
    Abstract: Low-temperature techniques for doping of Cu interconnects based on interfacially-assisted thermal diffusion are provided. In one aspect, a method of forming doped copper interconnects includes the steps of: patterning at least one trench in a dielectric material; forming a barrier layer lining the trench; forming a metal liner on the barrier layer; depositing a seed layer on the metal liner; plating a Cu fill into the trench to form Cu interconnects; removing a portion of a Cu overburden to access an interface between the metal liner and the Cu fill; depositing a dopant layer; and diffusing a dopant(s) from the dopant layer along the interface to form a Cu interconnect doping layer between the metal liner and the Cu fill. Alternatively, the overburden and the barrier layer/metal liner can be completely removed, and the dopant layer deposited selectively on the Cu fill. An interconnect structure is also provided.
    Type: Application
    Filed: December 18, 2018
    Publication date: May 16, 2019
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Chao-Kun Hu, Takeshi Nogami, Deepika Priyadarshini, Michael Rizzolo
  • Publication number: 20190148637
    Abstract: A method is presented for forming a semiconductor device. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form a plurality of trenches for receiving a first conducting material, forming a resistive switching memory element over at least one trench of the plurality of trenches, the resistive switching memory element having a conducting cap formed thereon, and depositing a dielectric cap over the trenches. The method further includes etching portions of the insulating layer to expose a section of the dielectric cap formed over the resistive switching memory element, etching the exposed section of the dielectric cap to expose the conducting cap of the resistive switching memory element, and forming a barrier layer in direct contact with the exposed section of the conducting cap.
    Type: Application
    Filed: November 16, 2017
    Publication date: May 16, 2019
    Inventors: Takashi Ando, Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Chih-Chao Yang
  • Patent number: 10290541
    Abstract: A semiconductor structure includes a dielectric layer having a trench formed therein and a barrier layer formed on a bottom and sidewalls of the trench, and on a top surface of the dielectric layer. The trench comprises a flared top gap opening and additional area at the bottom such that the top and bottom of the trench are wider than sidewalls of the trench. A thickness of the barrier layer on the bottom of the trench and on the top surface of the dielectric layer is controlled using one or more cycles comprising forming an oxidized layer using a neutral beam oxidation and removing the oxidized layer using an etching process, such that the thickness of the barrier layer on the bottom of the trench and on the top surface of the dielectric layer is substantially the same as the thickness of the barrier layer on sidewalls of the trench.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: May 14, 2019
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Cornelius Brown Peethala, Michael Rizzolo, Chih-Chao Yang
  • Patent number: 10276434
    Abstract: Semiconductor devices and methods to fabricate the devices are provided. For example, a semiconductor device includes a back-end-of-line (BEOL) structure formed on a semiconductor substrate. The BEOL structure further includes at least one metallization layer comprising a pattern of elongated parallel metal lines. The pattern of elongated metal lines comprises a plurality of metal lines having a minimum width and at least one wider metal line having a width which is greater than the minimum width.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: April 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Hsueh-Chung Chen, James Kelly, Yann Mignot, Cornelius Brown Peethala, Lawrence A. Clevenger
  • Patent number: 10276190
    Abstract: Monitoring and analysis of a user's speech to detect symptoms of a mental health disorder by continuously monitoring a user's speech in real-time to generate audio data based, transcribing the audio data to text and analyzing the text of the audio data to determine a sentiment of the audio data is disclosed. A trained machine learning model may be applied to correlate the text and the determined sentiment to clinical information associated with symptoms of a mental health disorder to determine whether the symptoms are a symptom event. The initial determination may be transmitted to a second device to determine (and/or verify) whether or not the symptom event was falsely recognized. The trained machine learning model may be updated based on a response from the second device.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: April 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Maryam Ashoori, Benjamin D. Briggs, Lawrence A. Clevenger, Leigh Anne H. Clevenger
  • Patent number: 10276053
    Abstract: Techniques for motivating a user during a workout using different coaching styles are provided. In one aspect, a method for motivational coaching of a user during workout sessions includes the steps of: selecting a coaching style for the user based on input from the user and from coaching styles used for at least one other user; determining, during a workout session, whether the coaching style should be changed to enhance performance of the user based on data obtained from the user via a mobile device worn by the user; changing the coaching style if it is determined that the coaching style should be changed to enhance performance of the user; continuing with a current coaching style if it is determined that the coaching style should not be changed; and providing feedback to the user during the workout session based on the coaching style.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: April 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Jonathan H. Connell, II, Nalini K. Ratha, Michael Rizzolo
  • Publication number: 20190122574
    Abstract: A computer-implemented method, a computer program product, and an incremental learning system are provided for language learning and speech enhancement. The method includes transforming acoustic utterances uttered by an individual into textual representations thereof, by a voice-to-language processor configured to perform speech recognition. The method further includes accelerating speech development in the individual, by an incremental learning system that includes the voice-to-language processor and that processes the acoustic utterances using natural language processing and analytics to determine and incrementally provide new material to the individual for learning.
    Type: Application
    Filed: October 25, 2017
    Publication date: April 25, 2019
    Inventors: Mahmoud Amin, Zhenxing Bi, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Christopher J. Penny, Krishna R. Tunga, Loma Vaishnav
  • Publication number: 20190122177
    Abstract: A delivery system is provided. In the delivery system, drones deliver items in a serviced area and charging stations are distributed throughout the serviced area. Each charging station is configured to charge one or more of the drones. The delivery system further includes a processor that is communicative with at least the charging stations. The processor is configured to dynamically route delivery operations of each of the drones in accordance with one or more parameters. The processor is further configured to communicate with individuals involved with the delivery operations in accordance with any of the charging stations being associated with the delivery operations.
    Type: Application
    Filed: October 19, 2017
    Publication date: April 25, 2019
    Inventors: BENJAMIN D. BRIGGS, LAWRENCE A. CLEVENGER, LEIGH A. CLEVENGER, CHRISTOPHER J. PENNY, MICHAEL RIZZOLO, ALDIS G. SIPOLINS
  • Publication number: 20190122911
    Abstract: One or more processors determine a predicted sorting bin of a semiconductor device, based on measurement and test data performed on the semiconductor device subsequent to a current metallization layer. A current predicted sorting bin and a target soring bin are determined by a machine learning model for the semiconductor device; the target bin include higher performance semiconductor devices than the predicted sorting bin. The model determines a performance level improvement attainable by adjustments made to process parameters of subsequent metallization layers of the semiconductor device. Adjustments to process parameters are generated, based on measurement and test data of the current metallization layer of semiconductor device, and the adjustment outputs for the process parameters of the subsequent metallization layers of the semiconductor device are made available to the one or more subsequent metallization layer processes by a feed-forward mechanism.
    Type: Application
    Filed: October 24, 2017
    Publication date: April 25, 2019
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Nicholas A. Lanzillo, Michael Rizzolo, Theodorus E. Standaert, James Stathis
  • Publication number: 20190115421
    Abstract: A semiconductor structure that includes a resistor that is located within an interconnect dielectric material layer of an interconnect level is provided. The resistor includes a diffusion barrier material that is present at a bottom of a feature that is located in the interconnect dielectric material layer. In some embodiments, the resistor has a topmost surface that is located entirely beneath a topmost surface of the interconnect dielectric material layer. In such an embodiment, the resistor is provided by removing sidewall portions of a diffusion barrier liner that surrounds a metal-containing structure. The removal of the sidewall portions of the diffusion barrier liner reduces the parasitic noise that is contributed to the sidewall portions of a resistor that includes such a diffusion barrier liner. Improved precision can also be obtained since sidewall portions may have a high thickness variation which may adversely affect the resistor's precision.
    Type: Application
    Filed: November 17, 2017
    Publication date: April 18, 2019
    Inventors: Baozhen Li, Kirk Peterson, John Sheets, Lawrence A. Clevenger, Junli Wang, Chih-Chao Yang
  • Publication number: 20190114671
    Abstract: Three-dimensional positional spatial olfaction for virtual marketing associates a product with a product location within a virtual reality environment and identifies a product aroma associated with the product. A distance and a direction from the product location to a positional presence of a participant within the virtual reality environment is determined, and the product aroma is delivered to the participant in accordance with the distance and the direction. Delivery of the product aroma to the participant in accordance with the distance and the direction is used to lead the participant through the virtual reality environment to the product location where an interface for obtaining a physical copy of the product is displayed to the participant.
    Type: Application
    Filed: October 13, 2017
    Publication date: April 18, 2019
    Inventors: Benjamin D. BRIGGS, Lawrence A. CLEVENGER, Leigh Anne H. CLEVENGER, Christoper J. PENNY, Michael RIZZOLO, Aldis SIPOLINS
  • Publication number: 20190115420
    Abstract: A semiconductor structure that includes a resistor that is located within an interconnect dielectric material layer of an interconnect level is provided. The resistor includes a diffusion barrier material that is present at a bottom of a feature that is located in the interconnect dielectric material layer. In some embodiments, the resistor has a topmost surface that is located entirely beneath a topmost surface of the interconnect dielectric material layer. In such an embodiment, the resistor is provided by removing sidewall portions of a diffusion barrier liner that surrounds a metal-containing structure. The removal of the sidewall portions of the diffusion barrier liner reduces the parasitic noise that is contributed to the sidewall portions of a resistor that includes such a diffusion barrier liner. Improved precision can also be obtained since sidewall portions may have a high thickness variation which may adversely affect the resistor's precision.
    Type: Application
    Filed: November 17, 2017
    Publication date: April 18, 2019
    Inventors: Baozhen Li, Kirk Peterson, John Sheets, Lawrence A. Clevenger, Junli Wang, Chih-Chao Yang
  • Publication number: 20190115418
    Abstract: A semiconductor structure that includes a resistor that is located within an interconnect dielectric material layer of an interconnect level is provided. The resistor includes a diffusion barrier material that is present at a bottom of a feature that is located in the interconnect dielectric material layer. In some embodiments, the resistor has a topmost surface that is located entirely beneath a topmost surface of the interconnect dielectric material layer. In such an embodiment, the resistor is provided by removing sidewall portions of a diffusion barrier liner that surrounds a metal-containing structure. The removal of the sidewall portions of the diffusion barrier liner reduces the parasitic noise that is contributed to the sidewall portions of a resistor that includes such a diffusion barrier liner. Improved precision can also be obtained since sidewall portions may have a high thickness variation which may adversely affect the resistor's precision.
    Type: Application
    Filed: October 13, 2017
    Publication date: April 18, 2019
    Inventors: Baozhen Li, Kirk Peterson, John Sheets, Lawrence A. Clevenger, Junli Wang, Chih-Chao Yang
  • Publication number: 20190115419
    Abstract: A semiconductor structure that includes a resistor that is located within an interconnect dielectric material layer of an interconnect level is provided. The resistor includes a diffusion barrier material that is present at a bottom of a feature that is located in the interconnect dielectric material layer. In some embodiments, the resistor has a topmost surface that is located entirely beneath a topmost surface of the interconnect dielectric material layer. In such an embodiment, the resistor is provided by removing sidewall portions of a diffusion barrier liner that surrounds a metal-containing structure. The removal of the sidewall portions of the diffusion barrier liner reduces the parasitic noise that is contributed to the sidewall portions of a resistor that includes such a diffusion barrier liner. Improved precision can also be obtained since sidewall portions may have a high thickness variation which may adversely affect the resistor's precision.
    Type: Application
    Filed: November 17, 2017
    Publication date: April 18, 2019
    Inventors: Baozhen Li, Kirk Peterson, John Sheets, Lawrence A. Clevenger, Junli Wang, Chih-Chao Yang
  • Patent number: 10256145
    Abstract: A method of forming a semiconductor device includes forming a sacrificial layer in a first contact hole of a first dielectric layer, forming a second dielectric layer on the first dielectric layer, and forming a second contact hole in the second dielectric layer, the second contact hole being aligned with the first contact hole, removing the sacrificial layer from the first contact hole, and forming a copper contact in the first and second contact holes.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: April 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Baozhen Li, Kirk David Peterson, John E. Sheets, II, Junli Wang, Chih-Chao Yang
  • Patent number: 10256185
    Abstract: A method for fabricating a semiconductor structure includes the following steps. A substrate including a dielectric material is formed. A surface of the substrate is molecularly modified to convert the surface of the substrate to a nitrogen-enriched surface. A metal layer is deposited on the molecularly modified surface of the substrate interacting with the molecularly modified surface to form a nitridized metal layer.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Roger A. Quon, Hosadurga K. Shobha, Terry A. Spooner, Wei Wang, Chih-Chao Yang
  • Patent number: 10256191
    Abstract: A semiconductor device is provided and includes first and second dielectrics, first and second conductive elements, a self-formed-barrier (SFB) and a liner. The first and second dielectrics are disposed with one of first-over-second dielectric layering and second-over-first dielectric layering. The first and second conductive elements are respectively suspended at least partially within a lower one of the first and second dielectrics and at least partially within the other one of the first and second dielectrics. The self-formed-barrier (SFB) is formed about a portion of one of the first and second conductive elements which is suspended in the second dielectric. The liner is deposited about a portion of the other one of the first and second conductive elements which is partially suspended in the first dielectric.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: April 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Nicholas A. Lanzillo, Takeshi Nogami, Christopher J. Penny, Michael Rizzolo
  • Patent number: 10242911
    Abstract: A semiconductor device includes a first trench on a mandrel line through a top mask layer and stopping at a middle mask layer; and a second trench on a non-mandrel line through the top mask layer and stopping at the middle mask layer. A spacer material is removed from a structure resulting from etching the first trench and the second trench. The device includes a first via structure, formed using a removable material, in the first trench; a second via structure, formed using a removable material, in the second trench; an air-gap formed in a third trench created at a location of the spacer; a fourth trench formed by etching, to remove the first via structure and a first portion of a bottom mask layer under the first via structure; and a self-aligned line-end via on the mandrel line formed by filling the fourth trench with a conductive metal.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Carl J. Radens, John H. Zhang