Patents by Inventor Lawrence A. Clevenger

Lawrence A. Clevenger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10672984
    Abstract: A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming a plurality of conductive lines within an interlayer dielectric (ILD), forming a RRAM stack including a bottom electrode, a top electrode, and a bi-layer hardmask, forming a low-k dielectric layer over the RRAM stack, removing a first layer of the bi-layer hardmask during a via opening, and removing a second layer of the bilayer hardmask concurrently with a plurality of sacrificial layers formed over the low-k dielectric layer.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Michael Rizzolo, Lawrence A. Clevenger, Shyng-Tsong Chen
  • Publication number: 20200160228
    Abstract: Embodiments of the invention provide a computer-implemented method of generating individualized strategies for a group of team members pursing a team objective based on an optimized team strategy. A team objective and a plurality of inputs associated with a plurality of team members is received at a strategy engine. A training model is applied to the plurality of inputs from the first plurality of team members to generate a plurality of individualized strategies for the first plurality of team members to achieve the team objective. An optimized team strategy based on the plurality of individualized strategies is generated and the individualized strategies are communicated to each team member wherein each team member pursuing their individualized strategy leads to achieving the team objective.
    Type: Application
    Filed: November 15, 2018
    Publication date: May 21, 2020
    Inventors: Mahmoud Amin, Zhenxing Bi, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Krishna R. Tunga
  • Publication number: 20200161239
    Abstract: Techniques facilitating back end of line electrical fuse structure and method of fabrication are provided. A device can comprise a first metal interconnect formed in a dielectric layer of a semiconductor chip. The device can also comprise a second metal interconnect formed in the dielectric layer and adjacent to the first metal interconnect. Further, the device can comprise a vertical electrical fuse element comprising a first portion of a conductive material deposited on a first surface of the first metal interconnect and a second portion of the conductive material deposited on a second surface of the second metal interconnect. The vertical electrical fuse element can comprise a first region comprising a first thickness and a second region comprising a second thickness different than the first thickness.
    Type: Application
    Filed: January 24, 2020
    Publication date: May 21, 2020
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Chih-Chao Yang
  • Publication number: 20200161175
    Abstract: Back end of line metallization structures and processes of fabricating the metallization structures generally include a top via integration scheme. The top via integration scheme integrally forms the via on top of trench. Thus, the via is fully aligned and can be of a desired critical dimension.
    Type: Application
    Filed: November 19, 2018
    Publication date: May 21, 2020
    Inventors: Chih-Chao Yang, Lawrence A. Clevenger, Benjamin D. Briggs, Brent Anderson
  • Patent number: 10658233
    Abstract: Techniques for dielectric damage-free interconnects are provided. In one aspect, a method for forming a Cu interconnect structure includes: forming a via and trench in a dielectric over a metal line M1; depositing a first barrier layer into the via and trench; removing the first barrier layer from the via and trench bottoms using neutral beam oxidation, and removing oxidized portions of the first barrier layer such that the first barrier layer remains along only sidewalls of the via and trench; depositing Cu into the via in direct contact with the metal line M1 to form a via V1; lining the trench with a second barrier layer; and depositing Cu into the trench to form a metal line M2. The second barrier layer can instead include Mn or optionally CuMn so as to further serve as a seed layer. A Cu interconnect structure is also provided.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Koichi Motoyama, Benjamin D. Briggs, Gangadhara Raja Muthinti, Cornelius Brown Peethala, Lawrence A. Clevenger
  • Patent number: 10657677
    Abstract: Embodiments include methods, systems, and computer program products for remediating a color vision deficiency. Aspects include receiving a time dependent location information for a user. Aspects also include receiving images of a plurality of objects, wherein each of the plurality of objects corresponds to the time dependent location information and, for each of the plurality of objects, identifying an object type and an object color. Aspects also include determining a number of distinguishable colors required to remediate a color vision deficiency and a number of available colors and overlaying one of the plurality of objects with an available color responsive to a determination that the number of distinguishable colors does not exceed the number of available colors.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: May 19, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yuk L. Chan, Lawrence A. Clevenger, Alain Loiseau, Deepti M. Naphade
  • Patent number: 10658235
    Abstract: Metal interconnect structures are reworked to address possible voids or other defects. Etching of initially deposited interconnect metal to open voids is followed by reflow to accumulate interconnect metal at the bottoms of trenches. Additional interconnect metal is deposited over the initially deposited interconnect metal by electroplating and/or electroless plating. Additional diffusion barrier material may be deposited and patterned prior to deposition of the additional interconnect material.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Prasad Bhosale, Terry A. Spooner, Chih-Chao Yang, Lawrence A. Clevenger
  • Patent number: 10658585
    Abstract: Methods and devices are provided for fabricating a resistive random-access array having dedicated electroforming contacts. A lower conductive line is formed on an interlayer dielectric layer. A lower electrode is formed on the lower conductive line. An isolation layer is formed having an upper surface which is coplanar with an upper surface of the lower electrode. A stack structure including a metal-oxide layer and upper electrode is formed on the lower electrode. Insulating spacers are formed on sidewalls of the stack structure. The lower electrode, and stack structure form a resistive memory cell, wherein a footprint of the lower electrode is greater than that of the upper electrode. An upper conductive line contacts the upper electrode, and is arranged orthogonal to the lower conductive line. A dedicated electroforming contact contacts an extended portion of the lower electrode which extends past a cross-point of the upper and lower conductive lines.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Lawrence A. Clevenger, Chih-Chao Yang, Benjamin D. Briggs
  • Patent number: 10651078
    Abstract: A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: May 12, 2020
    Assignee: Tessera, Inc.
    Inventors: Christopher J. Penny, Benjamin D. Briggs, Huai Huang, Lawrence A. Clevenger, Michael Rizzolo, Hosadurga Shobha
  • Publication number: 20200144187
    Abstract: Direct bonding heterogeneous integration packaging structures and processes include a packaging substrate with first and second opposing surfaces. A trench or a pedestal is provided in the first surface. A bridge is disposed in the trench or is adjacent the pedestal sidewall, wherein the bridge includes an upper surface coplanar with the first surface of the package substrate. At least two chips in a side by side proximal arrangement overly the bridge and the packaging substrate, wherein the bridge underlies peripheral edges of the at least two chips in the side by side proximal arrangement. The at least two chips include a plurality of electric connections that are directly coupled to corresponding electrical connections on the bridge and on the packaging substrate.
    Type: Application
    Filed: January 9, 2020
    Publication date: May 7, 2020
    Inventors: Kamal K. Sikka, Jon A. Casey, Joshua Rubin, Arvind Kumar, Dinesh Gupta, Charles L. Arvin, Mark W. Kapfhammer, Steve Ostrander, Maryse Cournoyer, Valérie A. Oberson, Lawrence A. Clevenger
  • Publication number: 20200135635
    Abstract: Techniques that facilitate integration of artificial intelligence devices are provided. In one example, a device includes a first dual-damascene layer, a second dual-damascene layer and an artificial intelligence memory device. The first dual-damascene layer comprises a first set of copper connections formed in first dielectric material. The second dual-damascene layer that comprises a second set of copper connections formed in second dielectric material. The artificial intelligence memory device is integrated between the first dual-damascene layer and the second dual-damascene layer. A through-level via (TLV) electrical connection associated with the artificial intelligence memory device provides an interconnection between the first set of copper connections and the second set of copper connections.
    Type: Application
    Filed: October 31, 2018
    Publication date: April 30, 2020
    Inventors: Hsueh-Chung Chen, Lawrence A. Clevenger, Fee Li Lie, Effendi Leobandung
  • Publication number: 20200136028
    Abstract: A semiconductor structure includes a memory element disposed on a first metal layer. A first cap layer is disposed on the first metal layer and sidewalls of the memory element. A first dielectric layer is disposed on a top surface of the first cap layer on the first metal layer and a portion of the first cap layer on the sidewalls of the memory element. A second metal layer is disposed on the first dielectric layer and sidewalls of the first cap layer. A second cap layer is disposed on a top surface of the second metal layer. A second dielectric layer is disposed on the second cap layer. A via is in the second dielectric layer and exposes a top surface of the memory element. A third metal layer is disposed on the second dielectric layer and in the via.
    Type: Application
    Filed: October 8, 2019
    Publication date: April 30, 2020
    Inventors: Nicholas A. Lanzillo, Benjamin D. Briggs, Chih-Chao Yang, Hsueh-Chung Chen, Lawrence A. Clevenger
  • Publication number: 20200135537
    Abstract: A method and structure of forming air gaps with a sidewall image transfer process such as self-aligned double patterning to reduce capacitance and resistance. In these methods and structures, the spacer is a metal.
    Type: Application
    Filed: October 31, 2018
    Publication date: April 30, 2020
    Inventors: Hsueh-Chung Chen, James Kelly, Yann Mignot, Cornelius Brown Peethala, Lawrence A. Clevenger
  • Publication number: 20200135560
    Abstract: A method for manufacturing a semiconductor device includes forming a conductive via extending vertically from a conductive layer, and depositing a first dielectric layer on the conductive layer and on lateral sides the conductive via. In the method, the conductive via is recessed with respect to a top surface of the first dielectric layer. An etch stop layer is deposited on the top surface of the first dielectric layer and on a top surface of the conductive via, and a second dielectric layer is deposited on the etch stop layer. The method also includes removing portions of the etch stop layer and the second dielectric layer to create a plurality of trenches spaced apart from each other. A trench of the plurality of trenches is formed over and exposes at least part of the conductive via, and a conductive material is deposited in the plurality of trenches.
    Type: Application
    Filed: October 29, 2018
    Publication date: April 30, 2020
    Inventors: Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Benjamin D. Briggs
  • Patent number: 10636738
    Abstract: A method of increasing the surface area of a contact to an electrical device that in one embodiment includes forming a contact stud extending through an intralevel dielectric layer to a component of the electrical device, and selectively forming a contact region on the contact stud. The selectively formed contact region has an exterior surface defined by a curvature and has a surface area that is greater than a surface area of the contact stud. An interlevel dielectric layer is formed on the intralevel dielectric layer, wherein an interlevel contact extends through the interlevel dielectric layer into direct contact with the selectively formed contact region.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: April 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, Terry A. Spooner, Junli Wang
  • Publication number: 20200125969
    Abstract: The present invention provides for a cognitive system using an autonomous vehicle includes a plurality of sensors configured to obtain the weather forecast for a pollution detectable area; a cognitive input to determine the pollution detectable area having highest sensitivity of pollution; a light detecting and ranging system configured to spatially probe pollution levels distributed in the pollution detectable area; an evaluation system to evaluate the probed pollution levels in the pollution detectable area; and a recommendation system for recommending an action to be taken based on evaluation system results of the probed pollution levels in the pollution detectable area, wherein the pollution levels are detected based light emitted by the light detecting and ranging system.
    Type: Application
    Filed: October 19, 2018
    Publication date: April 23, 2020
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Michael Rizzolo
  • Publication number: 20200126854
    Abstract: Techniques for dielectric damage-free interconnects are provided. In one aspect, a method for forming a Cu interconnect structure includes: forming a via and trench in a dielectric over a metal line M1; depositing a first barrier layer into the via and trench; removing the first barrier layer from the via and trench bottoms using neutral beam oxidation, and removing oxidized portions of the first barrier layer such that the first barrier layer remains along only sidewalls of the via and trench; depositing Cu into the via in direct contact with the metal line M1 to form a via V1; lining the trench with a second barrier layer; and depositing Cu into the trench to form a metal line M2. The second barrier layer can instead include Mn or optionally CuMn so as to further serve as a seed layer. A Cu interconnect structure is also provided.
    Type: Application
    Filed: October 17, 2018
    Publication date: April 23, 2020
    Inventors: Koichi Motoyama, Benjamin D. Briggs, Gangadhara Raja Muthinti, Cornelius Brown Peethala, Lawrence A. Clevenger
  • Patent number: 10629478
    Abstract: A method of forming a semiconductor device includes forming a dielectric spacer along sidewalls of a plurality of interconnect openings extending through a sacrificial dielectric layer and a first dielectric layer until a top portion of a first conductive material, the dielectric spacer includes a dielectric material having a dielectric constant higher than a dielectric constant of the sacrificial dielectric layer and higher than a dielectric constant of the first dielectric layer, conformally depositing a barrier liner within the plurality of interconnect openings above and in direct contact with the dielectric spacer, filling the interconnect openings with a second conductive material, removing the sacrificial dielectric layer to expose portions of the dielectric spacer above the first dielectric layer, and reducing a thickness of exposed portions of the dielectric spacer.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Huai Huang, Christopher J. Penny, Michael Rizzolo, Hosadurga Shobha
  • Patent number: 10629529
    Abstract: A semiconductor device includes a porous dielectric layer including a recessed portion, a conductive layer formed in the recessed portion, and a cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the cap layer.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: April 21, 2020
    Assignee: Tessera, Inc.
    Inventors: Benjamin David Briggs, Lawrence A. Clevenger, Bartlet H. Deprospo, Huai Huang, Christopher J. Penny, Michael Rizzolo
  • Patent number: 10629009
    Abstract: An unmanned vehicle is identified. One or more specifications of the unmanned vehicle are retrieved in response to the identification. A first characteristic of the unmanned vehicle is observed. The observed first characteristic is compared to the retrieved specifications. A compliance standard of the unmanned vehicle is determined. The determination is based on the comparison.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yuk L. Chan, Eileen P. Tedesco, Kyle Gilbertson, Daniel F. Hogerty, Lawrence A. Clevenger, Benjamin D. Briggs