Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first device layer on top of a backside back-end-of-line (BEOL) structure; a middle BEOL structure on top of the first device layer, the middle BEOL structure including multiple layers of small pitch wires and multiple layers of large pitch wires on top of the multiple layers of small pitch wires; a second device layer on top of the middle BEOL structure; a frontside BEOL structure on top of the second device layer; a first type via connection from the second device layer to the multiple layers of small pitch wires; and a second type and a third type via connection form the second device layer to the multiple layers of large pitch wires. A method of forming the same is also provided.

Abstract: A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.

Abstract: Embodiments of present invention provide a semiconductor structure. The structure includes a first cell unit including a first set of field-effect-transistors (FETs), a first cell boundary made of a first gate cut region, and a second cell boundary made of a second gate cut region; a second cell unit including a second set of FETs, a third cell boundary made of a third gate cut region, and a fourth cell boundary made of the first gate cut region; and a third cell unit including a third set of FETs, a fifth cell boundary made of the second gate cut region, and a sixth cell boundary made of a fourth gate cut region, where the first and third gate cut regions have a first width and the second and fourth gate cut region has a second width larger than the first width. A method of forming the same is also provided.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a plurality of lower metal lines in a first metal level; a transition via directly on top of the plurality of lower metal lines; and an upper metal line directly on top of the transition via and the upper metal line being in a second metal level and orthogonal to the plurality of lower metal lines, where at least a first lower metal line of the plurality of lower metal lines has a recessed region and a rest region, the recessed region is directly underneath the transition via and filled with a dielectric material; and isolates the rest region of the first lower metal line from the transition via. A method of manufacturing the same is also provided.

Abstract: A semiconductor structure includes an interconnect wiring level having metal lines. An insulating cut shape is disposed through a run length of one of the metal lines wherein the insulating cut shape divides the one of the metal lines into electrically isolated nets.

Abstract: A semiconductor device includes a plurality of field effect transistors (FET) formed upon semiconductor fins. Each FET includes a gate disposed transversely upon a first portion of the fins of the FET, one or more source/drain regions disposed upon the fins and in contact with the gate, and an electrically isolating layer disposed adjacent to a second portion of the fins above the gate and the source/drain regions, the electrically isolating layer having an interface with the gate. The device further includes a buried power rail (BPR) disposed between otherwise adjacent FETs. The BPR includes a metal rail extending beyond the interface into the gate, and electrically isolating sidewalls separating the metal rail from the gate and the source/drain regions. The device also includes a via-buried power rail contact disposed adjacent to the electrically isolating sidewalls, in contact with the metal rail, and in contact with one source/drain region.

Abstract: A semiconductor device includes a prime active region and a barrier region within the active prime region to define a barrier across a depth of the active prime region. A bypass structure includes a contact connecting to a component within the active prime region and extending outside the active prime region, a metal layer connecting to the first contact outside the active prime region and a through via passing through the depth of the active prime region and connecting to a solder bump.

Abstract: A semiconductor structure comprising a substrate, a first metal layer on top of the substrate, a second metal layer on top of the first metal layer and a dielectric layer adjacent to the second metal layer and at least part of the first metal layer and on top of at least part of the first metal layer. The first metal layer includes a via. The width of the second metal layer is the same as the width of the via of the first metal layer.

Abstract: Embodiments provide metal tip-to-tip scaling for metal contacts. A structure includes a first metal line and a second metal line. The structure includes a spacer separating the first metal line from the second metal line, the spacer including a flat surface and curved tips, where the flat surface abuts the first metal line and the curved tips abut the second metal line.

Abstract: A semiconductor integrated circuit (IC) device includes a backside resistor and a back end of the line (BEOL) network. The backside resistor is located upon a backside of the semiconductor IC device and may be vertically located between a front end of line (FEOL) microdevice, such as a diode and/or a transistor, and the BEOL network. The backside resistor is connected to the backside BEOL network and may be utilized to route current between different conductive pathways within the backside BEOL network or between the backside BEOL network and a frontside BEOL network.

Abstract: Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a front-end-of-line (FEOL) including a first source/drain (S/D) adjacent to a first gate. A device may include a backside interconnect below the FEOL, with a plurality of signal lines and a plurality of power lines. A device may include an offset gate contact electrically connected between the first gate and a first signal line of the plurality of signal lines, wherein the offset gate contact is located directly below the first S/D.

Abstract: A semiconductor integrated circuit (IC) device includes a backside fuse structure and a backside contact. The backside fuse structure is located within the backside of the semiconductor IC device vertically between a transistor there above and a backside back end of the line (BEOL) network. The backside fuse structure includes a fuse wire and a deep via contact that is connected to both the fuse wire and to a frontside BEOL network. The backside contact is connected to the transistor, to the backside BEOL network, and to the fuse wire. The backside fuse structure may be in a non-programmed state or a programmed state. When in a non-programmed state, an open circuit exists that prevents current flow through the fuse wire or through the backside contact.

Abstract: A semiconductor integrated circuit (IC) device that includes a backside fuse structure. The backside fuse structure is located within the backside of the semiconductor IC device and may be vertically located between a microdevice and a backside back end of the line (BEOL) network. The backside fuse structure includes at least a fuse wire. The backside fuse structure may be in a non-programmed state or a programmed state. When in a non-programmed state, an open circuit exists that prevents current flow through the fuse wire. The backside fuse structure may be directly connected to a deep via contact and/or one or more conductive pathways within the backside BEOL network.

Abstract: Integrated chips include first lines, formed on an underlying substrate. Spacers are formed conformally on sidewalls of the plurality of lines. Etch stop remnants are positioned on the sidewalls of the plurality of lines, between the spacers and the underlying substrate. Second lines are formed on the underlying substrate, between respective pairs of adjacent first lines.

Abstract: A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.

Abstract: A semiconductor device includes a first stack of nanowires above a substrate with a first gate structure over, around, and between the first stack of nanowires and a second stack of nanowires above the substrate with a second gate structure over, around, and between the second stack of nanowires. The device also includes a first source/drain region contacting a first number of nanowires of the first nanowire stack and a second source/drain region contacting a second number of nanowires of the second nanowire stack such that the first number and second number of contacted nanowires are different.

Abstract: A semiconductor device architecture includes a substrate and a device region including active components carried by the substrate. A plurality of tracks are on the substrate including conductive lines connecting power and signals to the active components in the device region. A first track includes a plurality of segments of a conductive line. A first segment in the first track delivers power to the device region. A second segment in the first track delivers a signal to the device region. The first segment and the second segment are arranged in the same first track.

Abstract: A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.

Abstract: A semiconductor device includes a plurality of gate caps over a plurality of gate regions, gate spacers over sidewalls of the plurality of gate regions and the plurality of gate caps, a backside contact under a first source and drain region and a dielectric cap over the first source and drain region. The first source and drain region is located between two adjacent gate regions of the plurality of gate regions.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a gate structure with a first portion having a first top surface and a second portion having a second top surface, the first top surface being above the second top surface; a dielectric cap layer on top of the second portion of the gate structure, the first portion of the gate structure being embedded in the dielectric cap layer; and a gate contact being above and substantially aligned with the first portion of the gate structure. A method of forming the same is also provided.