Abstract: A semiconductor device comprises a contact electrically connected to a source/drain region of a transistor and to a gate region of the transistor. A via is disposed along a side of the contact, wherein the via comprises a conductive material. A dielectric liner layer is disposed around at least a portion of the conductive material. The dielectric liner layer electrically isolates the contact from the conductive material, and the via contacts a bit-line.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a deep trench via in a double diffusion region between a first dummy metal gate and a second dummy metal gate; a frontside metal wire conductively connected to a top surface of the deep trench via through a frontside via; and a backside metal wire conductively connected to a bottom surface of the deep trench via through a backside via and a backside contact, where the frontside metal wire and the backside metal wire are not vertically aligned but parallel to each other, and directions of the frontside and backside metal wires are orthogonal to a length direction of the deep trench via. A method of forming the same is also provided.

Abstract: Embodiments of the invention include a first source region and a first drain region forming a first L-shaped layout. The first source and drain regions are formed on a bottom gate spacer material. Embodiments include a second source region and a second drain region forming a second L-shaped layout, the first L-shaped layout and the second L-shaped layout being interrupted by a gate. One of the first source and drain regions extends in a direction beyond the bottom gate spacer material to form the first L-shaped layout, wherein the direction is parallel to a lengthwise direction of the gate.

Abstract: A semiconductor interconnect structure and formation thereof. The semiconductor interconnect structure includes a first set of metal lines running along a first orientation, and a second set of metal lines having an insulating liner and running along a second orientation. The second set of metal lines are embedded within the first set of metal lines at respective cross points between the first and second set of metal lines, such that the second set of metal lines are located in a same metal level as the first set of metal lines.

Abstract: A first metal layer is deposited on a substrate. The first metal layer is etched to form one or more metal lines and expose portions of the substrate. A second metal layer is deposited on the exposed portions of the substrate between the one or more metal lines. The first metal layer is patterned to form one or more vertical vias. A dielectric layer is deposited on the exposed portions of the substrate between an exposed sidewalls of the first metal layer and an exposed sidewalls of the second metal layer.

Abstract: A semiconductor interconnect structure comprises a substrate, a plurality of metal lines disposed relative to the substrate and a plurality of first and second caps disposed on the metal lines wherein the first caps comprise a first dielectric material and the second caps comprise a second dielectric material different from the first dielectric material.

Abstract: A semiconductor device includes a gate cut disposed through a space between source/drain regions and corresponding source/drain contacts. The gate cut has a top surface above a top surface of the source/drain contacts. An asymmetric via is disposed on and wraps around a side of a top portion of the gate cut to connect one of the source/drain contacts to a power rail.

Abstract: A semiconductor device includes a gate metal and a gate extension disposed within a region between two transistors of opposite conductivity and connected to the gate metal. The gate extension extends toward a side of the semiconductor device having power rails. A gate cut is disposed within the gate metal and through the gate extension to cut the gate extension into portions that are electrically isolated from each other. Each of the portions of the gate extension is coupled to a backside power rail.

Abstract: A semiconductor structure with extended backside connections is provided.

Abstract: A semiconductor structure comprises a first device layer, a second device layer, and a plurality of interconnect wiring levels between the first device layer and the second device layer. The plurality of interconnect wiring levels comprise a first interconnect wiring level adjacent the first device layer, wherein wires of the first interconnect wiring level are spaced apart from each other at a first pitch, a second interconnect wiring level adjacent the second device layer, wherein wires of the second interconnect wiring level are spaced apart from each other at a second pitch, and at least a third interconnect wiring level between the first interconnect wiring level and the second interconnect wiring level, wherein wires of the third interconnect wiring level are spaced apart from each other at a third pitch. The third pitch is greater than the first pitch and the second pitch.

Abstract: An interconnect device has a first layer with a first metal line, a second metal line, and a third metal line, a second layer with a metal jumper and a metal via. The metal jumper is electrically connected to the first metal line and the second metal line. The metal via is electrically connected to the second metal line, and the metal jumper and the metal via are electrically isolated. The interconnect device further includes a third layer with a fourth metal line. The metal jumper is electrically isolated from the third metal line by a first dielectric region between the metal jumper and the third metal line.

Abstract: A microelectronic structure including an underlying device. An interconnect located on the underlying device. Interconnect includes a first Mx metal line and a second Mx metal line. The first Mx metal line is located adjacent to the second Mx metal line. A jumper connects the first Mx metal line to the second Mx metal line and the first Mx metal line extends higher than the jumper.

Abstract: Embodiments of the invention include a method for fabricating a semiconductor structure and the resulting structure. A plurality of semiconductor devices is formed, including a first semiconductor device and a second semiconductor device. A first contact is formed, where the first contact contacts: (i) the first semiconductor device and (ii) the second semiconductor device. A second contact and a third contact are formed, where the second contact contacts the first semiconductor device and the third contact contacts the second semiconductor device.

Abstract: A semiconductor device includes a first stack of nanowires above a substrate with a first gate structure over, around, and between the first stack of nanowires and a second stack of nanowires above the substrate with a second gate structure over, around, and between the second stack of nanowires. The device also includes a first source/drain region contacting a first number of nanowires of the first nanowire stack and a second source/drain region contacting a second number of nanowires of the second nanowire stack such that the first number and second number of contacted nanowires are different.

Abstract: A semiconductor structure includes a substrate, one or more nanosheet channel layers disposed over the substrate, and a dielectric bar attached to the one or more nanosheet channel layers, where the dielectric bar is not perpendicular to the substrate. The one or more nanosheet channel layers include a first set of one or more nanosheet channels attached to a first side of the dielectric bar and a second set of one or more nanosheet channels attached to a second side of the dielectric bar.

Abstract: A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first device layer on top of a backside back-end-of-line (BEOL) structure; a middle BEOL structure on top of the first device layer, the middle BEOL structure including multiple layers of small pitch wires and multiple layers of large pitch wires on top of the multiple layers of small pitch wires; a second device layer on top of the middle BEOL structure; a frontside BEOL structure on top of the second device layer; a first type via connection from the second device layer to the multiple layers of small pitch wires; and a second type and a third type via connection form the second device layer to the multiple layers of large pitch wires. A method of forming the same is also provided.

Abstract: Embodiments of present invention provide a semiconductor structure. The structure includes a first cell unit including a first set of field-effect-transistors (FETs), a first cell boundary made of a first gate cut region, and a second cell boundary made of a second gate cut region; a second cell unit including a second set of FETs, a third cell boundary made of a third gate cut region, and a fourth cell boundary made of the first gate cut region; and a third cell unit including a third set of FETs, a fifth cell boundary made of the second gate cut region, and a sixth cell boundary made of a fourth gate cut region, where the first and third gate cut regions have a first width and the second and fourth gate cut region has a second width larger than the first width. A method of forming the same is also provided.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a plurality of lower metal lines in a first metal level; a transition via directly on top of the plurality of lower metal lines; and an upper metal line directly on top of the transition via and the upper metal line being in a second metal level and orthogonal to the plurality of lower metal lines, where at least a first lower metal line of the plurality of lower metal lines has a recessed region and a rest region, the recessed region is directly underneath the transition via and filled with a dielectric material; and isolates the rest region of the first lower metal line from the transition via. A method of manufacturing the same is also provided.

Abstract: A semiconductor structure includes an interconnect wiring level having metal lines. An insulating cut shape is disposed through a run length of one of the metal lines wherein the insulating cut shape divides the one of the metal lines into electrically isolated nets.