Abstract: A method of forming fully aligned top vias is provided. The method includes forming a fill layer on a conductive line, wherein the fill layer is adjacent to one or more vias. The method further includes forming a spacer layer selectively on the exposed surface of the fill layer, wherein the top surface of the one or more vias is exposed after forming the spacer layer. The method further includes depositing an etch-stop layer on the exposed surfaces of the spacer layer and the one or more vias, and forming a cover layer on the etch-stop layer.

Abstract: A system for a touch screen interface that includes a coating including a plurality of a touch activated microchips; and a projector for projecting a light image onto the coating that is applied to a touch screen substrate. The system also includes an image calibrator that calibrates touch activated microchips in the coating to features of the light image projected onto the coating. The system further includes a receiver for receiving signal from the touch activated microchips when said feature of the light image is activated.

Abstract: A semiconductor device includes a plurality of field effect transistors (FET) formed upon semiconductor fins. Each FET includes a gate disposed transversely upon a first portion of the fins of the FET, one or more source/drain regions disposed upon the fins and in contact with the gate, and an electrically isolating layer disposed adjacent to a second portion of the fins above the gate and the source/drain regions, the electrically isolating layer having an interface with the gate. The device further includes a buried power rail (BPR) disposed between otherwise adjacent FETs. The BPR includes a metal rail extending beyond the interface into the gate, and electrically isolating sidewalls separating the metal rail from the gate and the source/drain regions. The device also includes a via-buried power rail contact disposed adjacent to the electrically isolating sidewalls, in contact with the metal rail, and in contact with one source/drain region.

Abstract: A skip-level through-silicon via structure is provided that enables low resistance via connection for backside power distribution by skipping one or more intermediate backside metal layers. The skip-level through-silicon via structure can enable a greater design flexibility for power grid. The skip-level through-silicon via structure has a large size that provides lower through-silicon via resistance as compared with conventional through-silicon via structures.

Abstract: An approach to provide a semiconductor structure using different two metal materials for interconnects in the middle of the line and the back end of the line metal layers of a semiconductor chip. The semiconductor structure includes the first metal material connecting both horizontally and vertically with the second metal material and the second metal material connecting both horizontally and vertically with the first metal material where the second metal material is more resistant to electromigration than the first metal material.

Abstract: 3D nanochannel interleaved devices for molecular manipulation are provided. In one aspect, a method of forming a device includes: forming a pattern on a substrate of alternating mandrels and spacers alongside the mandrels; selectively removing the mandrels from a front portion of the pattern forming gaps between the spacers; selectively removing the spacers from a back portion of the pattern forming gaps between the mandrels; filling i) the gaps between the spacers with a conductor to form first electrodes and ii) the gaps between the mandrels with the conductor to form second electrodes; and etching the mandrels and the spacers in a central portion of the pattern to form a channel (e.g., a nanochannel) between the first electrodes and the second electrodes, wherein the first electrodes and the second electrodes are offset from one another across the channel, i.e., interleaved. A device formed by the method is also provided.

Abstract: A method can include obtaining characteristic data for a wafer. The characteristic data can correspond to the wafer in a processed state and can include a set of stress values of the wafer. The wafer can include a front side, a back side opposite the front side, and a set of regions. The set of stress values can include a first stress value corresponding to a first region. In the processed state, one or more front-side processes can be completed on the front side of the wafer. The method can include determining that the first stress value exceeds a stress threshold and generating a compensation map. The compensation map can identify one or more regions for forming one or more trenches. The method can include initiating, based on the compensation map, a formation of a first trench on the back side of the wafer in the first region.

Abstract: Embodiments of the present invention are directed to fabrication methods and resulting interconnect structures having a conductive thin metal layer on a top via that promotes the selective growth of the next level interconnect lines (the line above). In a non-limiting embodiment of the invention, a first conductive line is formed in a dielectric layer. A via is formed on the first conductive line and a seed layer is formed on the via and the dielectric layer. A surface of the seed layer is exposed and a second conductive line is deposited onto the exposed surface of the seed layer. In a non-limiting embodiment of the invention, the second conductive line is selectively grown from the seed layer.

Abstract: Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a first power plane electrically connected to a first plurality of via-to-backside power planes (VBPPs), a second power plane, and a plurality of pass through vias electrically connecting the second power plane to a second plurality of VBPPs, wherein the plurality of pass through vias pass through the first power plane.

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A first field-effect transistor (FET) having a first source/drain region is formed. A second FET having a second source/drain region is formed, where the second FET is stacked above the first FET. A trench extending from above the second source/drain region to beneath the first source/drain region is formed, where the trench passes through portions of (i) the first source/drain region and (ii) the second source/drain region. A bottom contact is formed in the trench. A dielectric layer is formed in the trench, the dielectric layer on a top surface of the bottom contact. A top contact is formed in the trench, the top contact on a top surface of the dielectric layer.

Abstract: A semiconductor device includes a porous dielectric layer including a recessed portion, a conductive layer formed in the recessed portion, and a cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the cap layer.

Abstract: A phase change memory device is provided. The phase change memory device includes a phase change memory material within an electrically insulating wall, a first heater terminal in the electrically insulating wall, and two read terminals in the electrically insulating wall.

Abstract: An interconnect structure including a top via with a minimum line end extension comprises a cut filled with an etch stop material. The interconnect structure further comprises a line formed adjacent to the etch stop material. The interconnect structure further comprises a top via formed on the line adjacent to the etch stop material, wherein the top via utilizes the etch stop material to achieve minimum line extension.

Abstract: A non-volatile memory structure may include a phase change memory comprising a phase change material. The non-volatile memory structure may include a Schottky diode in series with the phase change memory, wherein a Schottky barrier of the Schottky diode is a surface of the phase change memory. This may be accomplished through a proper selection of materials for the contact of the phase change memory. This may create an integrated diode-memory structure which may control directionality of current without a penalty on the footprint of the structure.

Abstract: A method for forming a phase-change memory cell includes depositing a metal layer over a wafer such that the metal layer covers connection structures of the wafer. The method further includes removing a portion of the metal layer such that the connection structures of the wafer remain covered by a remaining portion of the metal layer. The method further includes forming a phase-change memory stack on a stack area of the remaining portion of the metal layer. The method further includes removing the remaining portion of the metal layer except in the stack area.

Abstract: Integrated chips include a dielectric layer that includes at least one trench and at least one plug region. A line is formed in the dielectric layer in the at least one trench and terminates at the plug region. A dielectric plug is formed in the plug region.

Abstract: A system for a touch screen interface that includes a coating including a plurality of a touch activated microchips; and a projector for projecting a light image onto the coating that is applied to a touch screen substrate. The system also includes an image calibrator that calibrates touch activated microchips in the coating to features of the light image projected onto the coating. The system further includes a receiver for receiving signal from the touch activated microchips when said feature of the light image is activated.

Abstract: Embodiments of present invention provide a semiconductor chip. The semiconductor chip includes a device layer having a first and a second circuit region; a frontside distribution network (FSDN) above the device layer and powering the first circuit region; and a backside distribution network (BSDN) below the device layer and powering the second circuit region, wherein the BSDN is electrically connected to the FSDN through the device layer and the FSDN is electrically connected to the first circuit region through one or more frontside metal layers, and wherein the BSDN is electrically connected to transistors of the second circuit region through the device layer.

Abstract: 3D nanochannel interleaved devices for molecular manipulation are provided. In one aspect, a method of forming a device includes: forming a pattern on a substrate of alternating mandrels and spacers alongside the mandrels; selectively removing the mandrels from a front portion of the pattern forming gaps between the spacers; selectively removing the spacers from a back portion of the pattern forming gaps between the mandrels; filling i) the gaps between the spacers with a conductor to form first electrodes and ii) the gaps between the mandrels with the conductor to form second electrodes; and etching the mandrels and the spacers in a central portion of the pattern to form a channel (e.g., a nanochannel) between the first electrodes and the second electrodes, wherein the first electrodes and the second electrodes are offset from one another across the channel, i.e., interleaved. A device formed by the method is also provided.

Abstract: A semiconductor device includes a first stack of nanowires above a substrate with a first gate structure over, around, and between the first stack of nanowires and a second stack of nanowires above the substrate with a second gate structure over, around, and between the second stack of nanowires. The device also includes a first source/drain region contacting a first number of nanowires of the first nanowire stack and a second source/drain region contacting a second number of nanowires of the second nanowire stack such that the first number and second number of contacted nanowires are different.