Patents by Inventor Lawrence A. Clevenger

Lawrence A. Clevenger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10150323
    Abstract: An anti-counterfeiting method, system, and non-transitory computer readable medium, include a production circuit configured to produce a Directed Self-Assembly (DSA) pattern including a unique pattern, an analysis circuit configured to analyze the unique pattern, an embedding circuit configured to embed the unique pattern on a document, and a verification circuit configured to verify that the unique pattern embedded on the document corresponds to the document.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: December 11, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin David Briggs, Lawrence A. Clevenger, Bartlet H. DeProspo, Michael Rizzolo
  • Publication number: 20180349220
    Abstract: Methods and systems for printing accurate three-dimensional structures include printing a three-dimensional structure according to an original three-dimensional model. The original three-dimensional model is adjusted to reduce measured differences between the printed three-dimensional structure and the original three-dimensional model. A three-dimensional structure is printed according to the adjusted three-dimensional model.
    Type: Application
    Filed: June 5, 2017
    Publication date: December 6, 2018
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Christopher J. Penny, Michael Rizzolo, Aldis G. Sipolins
  • Publication number: 20180350599
    Abstract: A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.
    Type: Application
    Filed: August 8, 2018
    Publication date: December 6, 2018
    Inventors: Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Nelson M. Felix, Sivananda K. Kanakasabapathy, Christopher J. Penny, Roger A. Quon, Nicole A. Saulnier
  • Publication number: 20180351596
    Abstract: A system for a touch screen interface that includes a coating including a plurality of a touch activated microchips; and a projector for projecting a light image onto the coating that is applied to a touch screen substrate. The system also includes an image calibrator that calibrates touch activated microchips in the coating to features of the light image projected onto the coating. The system further includes a receiver for receiving signal from the touch activated microchips when said feature of the light image is activated.
    Type: Application
    Filed: May 30, 2017
    Publication date: December 6, 2018
    Inventors: Maryam Ashoori, Benjamin D. Briggs, Justin A. Canaperi, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Michael Rizzolo, Spyridon Skordas
  • Publication number: 20180328977
    Abstract: Embodiments of the invention are directed to a semiconductor wafer test system. A non-limiting example of the test system includes a controller, a sensing system communicatively coupled to the controller, and a stress source communicatively coupled to the controller. The controller is configured to control the stress source to deliver an applied stress to a targeted stress area of a semiconductor wafer. The sensing system is configured to detect the applied stress and provide data of the applied stress to the controller. The controller is further configured to control the stress source based at least in part on the data of the applied stress.
    Type: Application
    Filed: May 10, 2017
    Publication date: November 15, 2018
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Nicholas A. Lanzillo, Michael Rizzolo, Theodorus E. Standaert, James H. Stathis
  • Publication number: 20180328979
    Abstract: Embodiments of the invention are directed to a semiconductor wafer test system. A non-limiting example of the test system includes a controller, a sensing system communicatively coupled to the controller, and a stress source communicatively coupled to the controller. The controller is configured to control the stress source to deliver an applied stress to a targeted stress area of a semiconductor wafer. The sensing system is configured to detect the applied stress and provide data of the applied stress to the controller. The controller is further configured to control the stress source based at least in part on the data of the applied stress.
    Type: Application
    Filed: November 6, 2017
    Publication date: November 15, 2018
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Nicholas A. Lanzillo, Michael Rizzolo, Theodorus E. Standaert, James H. Stathis
  • Patent number: 10128147
    Abstract: Semiconductor structures include a patterned interlayer dielectric overlaying a semiconductor substrate. The interlayer dielectric includes a first dielectric layer and at least one additional dielectric layer disposed on the first dielectric layer, wherein the patterned interlayer dielectric comprises at least one opening extending through the interlayer dielectric to the semiconductor substrate. Chemically enriched regions including ions of Si, P, B, N, O and combinations thereof are disposed in surfaces of the first dielectric layer and the at least one dielectric layer defined by the at least one opening. Also described are methods of for forming an interconnect structure in a semiconductor structure.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: November 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Roger A. Quon, Terry A. Spooner, Wei Wang, Chih-Chao Yang
  • Patent number: 10121661
    Abstract: A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: November 6, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Nelson M. Felix, Sivananda K. Kanakasabapathy, Christopher J. Penny, Roger A. Quon, Nicole A. Saulnier
  • Publication number: 20180315094
    Abstract: A computer implemented method and system for identifying advertisements targeted to individuals based on analysis of audio recordings. The method includes recording audio input from at least one media transmission, analyzing the recorded media audio to identify content of the at least one media transmission, recording audio input from at least one individual, analyzing the recorded individual audio to classify the at least one individual into at least one segment, analyzing the recorded individual audio to identify at least one sentiment related to the identified media content, analyzing the at least one sentiment in context with the identified media content and identifying at least one advertisement targeted to the at least one segment based on the contextual analysis.
    Type: Application
    Filed: November 29, 2017
    Publication date: November 1, 2018
    Inventors: Maryam Ashoori, Benjamin D. Briggs, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Michael Rizzolo
  • Publication number: 20180315703
    Abstract: A conductive interface includes a first conductor having a recessed area in least one surface. A dielectric layer has a trench positioned over the first conductor. A nitridized layer is formed on a top surface of the first conductor around the recessed area, to a depth on the first conductor that is shallower than a depth of the recessed area. A second conductor is formed in the trench and the recessed area to form a conductive contact with the first conductor.
    Type: Application
    Filed: June 21, 2018
    Publication date: November 1, 2018
    Inventors: Lawrence A. Clevenger, Roger A. Quon, Terry A. Spooner, Wei Wang, Chih -Chao Yang
  • Publication number: 20180315093
    Abstract: A computer implemented method and system for identifying advertisements targeted to individuals based on analysis of audio recordings. The method includes recording audio input from at least one media transmission, analyzing the recorded media audio to identify content of the at least one media transmission, recording audio input from at least one individual, analyzing the recorded individual audio to classify the at least one individual into at least one segment, analyzing the recorded individual audio to identify at least one sentiment related to the identified media content, analyzing the at least one sentiment in context with the identified media content and identifying at least one advertisement targeted to the at least one segment based on the contextual analysis.
    Type: Application
    Filed: May 1, 2017
    Publication date: November 1, 2018
    Inventors: Maryam Ashoori, Benjamin D. Briggs, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Michael Rizzolo
  • Patent number: 10115633
    Abstract: A method for producing self-aligned line end vias and the resulting device are provided. Embodiments include trench lines formed in a dielectric layer; each trench line including a pair of self aligned line end vias; and a high-density plasma (HDP) oxide, silicon carbide (SiC) or silicon carbon nitride (SiCNH) formed between each pair of self aligned line end vias, wherein the trench lines and self aligned line end vias are filled with a metal liner and metal.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: October 30, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John H. Zhang, Carl J. Radens, Lawrence A. Clevenger
  • Publication number: 20180307798
    Abstract: A delivery device includes a circuit for receiving an authentication signal. The delivery device contains a substance encapsulated therein. The delivery device determines whether a user is authenticated based upon the authentication signal and an identifier stored within the delivery device. The delivery device heats, responsive to determining that the user is not authenticated within a predetermined time period after the delivery device being ingested by the user, the substance encapsulated within the delivery device.
    Type: Application
    Filed: April 24, 2017
    Publication date: October 25, 2018
    Applicant: International Business Machines Corporation
    Inventors: Ira L. Allen, Gregory J. Boss, Lawrence A. Clevenger, Andrew R. Jones, Kevin C. McConnell, John E. Moore, JR.
  • Patent number: 10109579
    Abstract: A method of forming a semiconductor device, includes forming a conductive layer in a recessed portion of a porous dielectric layer, partially removing a top portion of the conductive layer while maintaining a height of the porous dielectric layer, forming a conformal cap layer on the porous dielectric layer and the conductive layer in the recessed portion, polishing the conformal cap layer to form a gap in the conformal cap layer, such that an upper surface of the porous dielectric layer is exposed through the gap and an upper surface of the conductive layer is protected by the cap layer, and performing a heat treatment to burn out a pore filler of the porous dielectric layer through the exposed upper surface of the porous dielectric layer.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: October 23, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin David Briggs, Lawrence A. Clevenger, Bartlet H. Deprospo, Huai Huang, Christopher J. Penny, Michael Rizzolo
  • Patent number: 10099108
    Abstract: Embodiments are directed to a support apparatus. The support apparatus might comprise a body configured to support an entity. The body might comprise a material that has a physical property. The support apparatus might further comprise a coupler system configured to couple electric current from a power source to the material. The material is arranged such that coupling an electric current to the material changes the physical property of the material. Embodiments are further directed to a method. The method might comprise forming one or more cavities in a support apparatus. The method might further comprise providing one or more couplers in electrical contact with each of the one or more channels. The method further comprises filling each of the one or more cavities with a fluid that has electrically changeable rigidity. Finally, the method might comprise connecting a power source to each of the one or more couplers.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: October 16, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Bartlet H. DeProspo, Michael Rizzolo
  • Publication number: 20180286750
    Abstract: A semiconductor device includes a first trench on a mandrel line through a top mask layer and stopping at a middle mask layer; and a second trench on a non-mandrel line through the top mask layer and stopping at the middle mask layer. A spacer material is removed from a structure resulting from etching the first trench and the second trench. The device includes a first via structure, formed using a removable material, in the first trench; a second via structure, formed using a removable material, in the second trench; an air-gap formed in a third trench created at a location of the spacer; a fourth trench formed by etching, to remove the first via structure and a first portion of a bottom mask layer under the first via structure; and a self-aligned line-end via on the mandrel line formed by filling the fourth trench with a conductive metal.
    Type: Application
    Filed: November 16, 2017
    Publication date: October 4, 2018
    Applicant: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Carl J. Radens, John H. Zhang
  • Publication number: 20180277433
    Abstract: A method for forming conductive structures for a semiconductor device includes depositing a reflow liner on walls of trenches formed in a dielectric layer and depositing a reflow material on the reflow liner. The reflow material is reflowed to collect in a lower portion of the trenches. The depositing and the reflowing steps are repeated until the trenches are aggregately filled with the reflow material. The reflow material is planarized to form conductive structures in the trenches.
    Type: Application
    Filed: March 1, 2018
    Publication date: September 27, 2018
    Inventors: Lawrence A. Clevenger, Su Chen Fan, Huai Huang, Koichi Motoyama, Wei Wang, Chih-Chao Yang
  • Publication number: 20180277432
    Abstract: A method for forming conductive structures for a semiconductor device includes depositing a reflow liner on walls of trenches formed in a dielectric layer and depositing a reflow material on the reflow liner. The reflow material is reflowed to collect in a lower portion of the trenches. The depositing and the reflowing steps are repeated until the trenches are aggregately filled with the reflow material. The reflow material is planarized to form conductive structures in the trenches.
    Type: Application
    Filed: November 15, 2017
    Publication date: September 27, 2018
    Inventors: Lawrence A. Clevenger, Su Chen Fan, Huai Huang, Koichi Motoyama, Wei Wang, Chih-Chao Yang
  • Publication number: 20180277482
    Abstract: Methods are provided for fabricating metallic interconnect structures having reduced electrical resistivity that is obtained by applying mechanical strain to the metallic interconnect structures, as well as semiconductor structures having metallic interconnect structures formed with permanent mechanical strain to provide reduced electrical resistivity. For example, a method includes forming a metallic interconnect structure in an interlevel dielectric (ILD) layer of a back-end-of-line (BEOL) structure of a semiconductor structure, and forming a stress layer in contact with the metallic interconnect structure. A thermal anneal process is performed to cause the stress layer to expand and apply compressive strain to the metallic interconnect structure and permanently deform at least a portion of the metallic interconnect structure into a stress memorized state of compressive strain.
    Type: Application
    Filed: November 13, 2017
    Publication date: September 27, 2018
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Nicholas A. Lanzillo, Michael Rizzolo, Theodorus E. Standaert
  • Patent number: 10083862
    Abstract: A method of forming a protective liner between a gate dielectric and a gate contact. The method may include; forming a finFET having a replacement metal gate (RMG) on one or more fins, the RMG includes a gate dielectric wrapped around a metal gate, an outer liner is on the sidewalls of the gate dielectric and on the fins; forming a gate contact trench by recessing the gate dielectric and the outer liner below a top surface of the metal gate in a gate contact region; forming a protective trench by further recessing the gate dielectric below a top surface of the outer liner; filling the protective trench with a protective liner; and forming a gate contact in the gate contact trench, where the protective liner is between the gate dielectric and the gate contact.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: September 25, 2018
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, Junli Wang