Abstract: A device includes a temperature-variable voltage controller, in which the temperature-variable voltage controller comprises: a voltage regulator; a process monitor circuit coupled to the voltage regulator, in which the process monitor circuit includes a ring oscillator, and a frequency counter coupled to an output of the ring oscillator; and a temperature-variable current source coupled to the voltage regulator so that, during operation, the output voltage of the voltage regulator is compensated based on a change in temperature of the temperature-variable current source.

Abstract: The disclosure relates to technology for generating multi-phase signals. An apparatus includes 2{circumflex over (?)}n phase signal generation stages. The apparatus also includes a controller configured to provide a mode input of each of the 2{circumflex over (?)}n stages with an active periodic binary signal with remaining inputs of each of the 2{circumflex over (?)}n stages provided with another periodic binary signal to collectively generate a 2{circumflex over (?)}n phase signal in a first mode.

Abstract: The disclosure relates to technology for generating multi-phase signals. An apparatus includes 2{circumflex over (?)}n phase signal generation stages. The apparatus also includes a controller configured to provide a mode input of each of the 2{circumflex over (?)}n stages with an active periodic binary signal with remaining inputs of each of the 2{circumflex over (?)}n stages provided with another periodic binary signal to collectively generate a 2{circumflex over (?)}n phase signal in a first mode.

Abstract: The disclosure relates to technology for shifting a frequency range of a signal. In one aspect, a circuit comprises a frequency mixer, a frequency synthesizer configured to generate an oscillator signal, a programmable driver, and a controller. The programmable driver is configured to receive the oscillator signal from the frequency synthesizer and to provide the oscillator signal to the oscillator input of the frequency mixer. The programmable driver is configured to have a variable drive strength. The controller is configured to control the drive strength of the programmable driver based on a frequency of the oscillator signal to adjust a rise time and a fall time of the oscillator signal at the oscillator input of the frequency mixer.

Abstract: Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.

Abstract: The disclosure relates to technology for shifting a frequency range of a signal. In one aspect, a circuit comprises a frequency mixer, a frequency synthesizer configured to generate an oscillator signal, a programmable driver, and a controller. The programmable driver is configured to receive the oscillator signal from the frequency synthesizer and to provide the oscillator signal to the oscillator input of the frequency mixer. The programmable driver is configured to have a variable drive strength. The controller is configured to control the drive strength of the programmable driver based on a frequency of the oscillator signal to adjust a rise time and a fall time of the oscillator signal at the oscillator input of the frequency mixer.

Abstract: The disclosure relates to technology for generating multi-phase signals. An apparatus includes 2{circumflex over (?)}n phase signal generation stages. The apparatus also includes a controller configured to provide a mode input of each of the 2{circumflex over (?)}n stages with an active periodic binary signal with remaining inputs of each of the 2{circumflex over (?)}n stages provided with another periodic binary signal to collectively generate a 2{circumflex over (?)}n phase signal in a first mode.

Abstract: Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.

Abstract: An apparatus comprises a plurality of selectable gain stages connected in parallel between a first bias voltage and ground, wherein each selectable gain stage comprises an amplification portion and a current steering portion, and wherein the current steering portion comprises a first selectable signal path connected between an output of the amplification portion and a signal output terminal, and a second selectable signal path connected between the output of the amplification portion and ground through a shunt device.

Abstract: The disclosure relates to technology for power supply for a voltage controller oscillator (VCO), where the power supply has a closed loop mode and an open loop mode. In closed loop mode, a peak detector circuit determines the amplitude of the output for the VCO, which is compared to a reference value in an automatic gain control loop. An input voltage for the VCO is determined based on a difference between the reference value and the output of the peak detector circuit. The peak detector circuit can be implemented using parasitic bipolar devices in an integrated circuit formed in a CMOS process. While operating in the closed loop mode, a controller monitors the input voltage and, when the input voltage is stabilized, the controller uses this input voltage value determined in open loop mode.

Abstract: The disclosure relates to technology for generating multi-phase signals. An apparatus includes 2{circumflex over (?)}n phase signal generation stages. The apparatus also includes a controller configured to provide a mode input of each of the 2{circumflex over (?)}n stages with an active periodic binary signal with remaining inputs of each of the 2{circumflex over (?)}n stages provided with another periodic binary signal to collectively generate a 2{circumflex over (?)}n phase signal in a first mode.

Abstract: The disclosure relates to technology for generating multi-phase signals. An apparatus includes 2{circumflex over (?)}n phase signal generation stages. The apparatus also includes a controller configured to provide a mode input of each of the 2{circumflex over (?)}n stages with an active periodic binary signal with remaining inputs of each of the 2{circumflex over (?)}n stages provided with another periodic binary signal to collectively generate a 2{circumflex over (?)}n phase signal in a first mode.

Abstract: The disclosure relates to technology for power supply for a voltage controller oscillator (VCO), where the power supply has a closed loop mode and an open loop mode. In closed loop mode, a peak detector circuit determines the amplitude of the output for the VCO, which is compared to a reference value in an automatic gain control loop. An input voltage for the VCO is determined based on a difference between the reference value and the output of the peak detector circuit. The peak detector circuit can be implemented using parasitic bipolar devices in an integrated circuit formed in a CMOS process. While operating in the closed loop mode, a controller monitors the input voltage and, when the input voltage is stabilized, the controller uses this input voltage value determined in open loop mode.

Abstract: An apparatus comprises a plurality of selectable gain stages connected in parallel between a first bias voltage and ground, wherein each selectable gain stage comprises an amplification portion and a current steering portion, and wherein the current steering portion comprises a first selectable signal path connected between an output of the amplification portion and a signal output terminal, and a second selectable signal path connected between the output of the amplification portion and ground through a shunt device.

Abstract: The disclosure relates to technology for shifting a frequency range of a signal. In one aspect, a circuit comprises a frequency mixer, a frequency synthesizer configured to generate an oscillator signal, a programmable driver, and a controller. The programmable driver is configured to receive the oscillator signal from the frequency synthesizer and to provide the oscillator signal to the oscillator input of the frequency mixer. The programmable driver is configured to have a variable drive strength. The controller is configured to control the drive strength of the programmable driver based on a frequency of the oscillator signal to adjust a rise time and a fall time of the oscillator signal at the oscillator input of the frequency mixer.

Abstract: An embodiment integrated circuit includes a switch and a conductive line over the switch. The switch includes a gate, a first source/drain region at a top surface of a semiconductor substrate, and a second source/drain region at the top surface of the semiconductor substrate. The first source/drain region and the second source/drain region are disposed on opposing sides of the gate. At least a portion of the first conductive line is aligned with the gate, and the first conductive line is electrically coupled to ground.

Abstract: An apparatus comprising a latch comprising a differential inverter configured to receive a differential input signal and generate a differential output signal, a pair of cross-coupled inverters coupled to the differential inverter, and a first clock switch configured to couple the differential inverter to a voltage source, a second clock switch configured to couple the differential inverter to a ground, wherein the first clock switch and the second clock switch are configured to receive a differential clock signal, and wherein the first clock switch and the second clock switch are both open or both closed depending on the differential clock signal, a second latch, wherein the first latch and the second latch are configured as a frequency divider, and a logic circuit coupled to each latch, wherein the logic circuits are configured to generate both an in-phase reference output signal and a quadrature output signal.

Abstract: An apparatus comprising a frequency divider comprising a first latch and a second latch coupled to the first latch in a toggle-flop configuration, and an output circuit comprising a first p-channel transistor, wherein the gate of the first p-channel transistor is configured to receive a clock signal, a first n-channel transistor, wherein the gate of the first n-channel transistor is coupled to the first latch, a second n-channel transistor connected in series with the first p-channel transistor and the first n-channel transistor and wherein the gate of the second n-channel transistor is configured to receive the clock signal, a second p-channel transistor, wherein the gate of the second p-channel transistor is configured to receive the clock signal, and a third n-channel transistor in series with the second p-channel transistor and the second n-channel transistor, wherein the output circuit is configured to generate a pair of in-phase reference signals.

Abstract: An apparatus comprising a frequency divider comprising a first latch configured to receive a first clock signal and a complement of the first clock signal and to generate a first latch first output, and a second latch coupled to the first latch in a toggle-flop configuration, a first output circuit comprising a p-channel transistor, wherein the gate of a p-channel transistor is configured to receive the first clock signal, and a n-channel transistor, wherein the drain of the p-channel transistor is directly connected to the drain of a n-channel transistor, wherein the gate of the n-channel transistor is configured to receive the first latch first output, wherein the source of the n-channel transistor is configured to receive the complement of the first clock signal, and wherein the first output circuit is configured to generate an in-phase reference signal, and a second output circuit configured to generate a quadrature signal.

Abstract: An apparatus comprising a latch comprising a differential inverter configured to receive a differential input signal and generate a differential output signal, a pair of cross-coupled inverters coupled to the differential inverter, and a first clock switch configured to couple the differential inverter to a voltage source, a second clock switch configured to couple the differential inverter to a ground, wherein the first clock switch and the second clock switch are configured to receive a differential clock signal, and wherein the first clock switch and the second clock switch are both open or both closed depending on the differential clock signal.